Kamal Kundu

* Validated post-silicon synthetic tests on SoC emulations and delivered first time right content. * Verified boot script (TAP Based tool to enable early boot stages to override fuses, workaround and bypass) with breaks at debug stages on Emulation to mock power-on. * Validated overclocking’s functional features on latest intel CPU and recovered issues in BIOS. * Correlated DFD features like VISA capture, scan dumps, Traces on silicon with emulation runs.

* Managed SoC Verification activities involving RTL, GLS verification and silicon validation. * Coordinated deliveries across multi-site teams design,PD,SIM,ATE,PTE teams and aligned delivery dates. * Improved test plan by mapping features to test cases and adding new tests from RMA learnings. * Assessed the risk with the design changes and reduced the ECOs going to netlist. * Organized weekly DV meetings to communicate bugs, methodology, design changes, issues, plan etc.

* Implemented common DV platform to validate 2 DUTs to reduce the NRE cost. * Migrated functional test vectors from TCMS foundry to Global Foundry using minimum head count. * Verified CPR (Core Power Reduction), RPM(resource power management) and slow speed peripherals (UART,I2C,SPI). * Coded new tests and vectors for ECO validation, characterization and testability improvement. * Parametrized the tests for DFD,CPR and LSP as these IPs have changed in every product. * Debugged Vmin/Fmax for CPU(ARM53,ARM57 and ARM72) and silicon and timing simulations. * Formal verification (VC formal) to verify register to signal (TLMM) connectivity and memory ACC. * Integrated compiled RTL, VIP, Drivers, VIF, Forces, vector environment and other test bench components. * Brought up GLS environment and resolved compilation, elaboration issues coming from netlist and SDFs * Brought up GLS models for ATPG’s simulations and added checkers to catch backdoor loads. * Booted and debugged 1st dead or alive tests from various processors in the SoC devices. * Integrated the Frequency Plans at SoC for RTL, Timing Simulations and ATE validation. * Finalized LPC (Low Pin Count) with design, FT and ATE teams to optimize pins which enabled maximum coverage with less pins to enable multisite testing there by reduced time and cost.

Post Silicon validation (ATE) * Powered on functional vectors on the HP 93k ATE platform for TSMC and Global foundry. * Engineered hooks for faster debug while balancing the tester time and vector memory. * Debugged critical failing vectors for function blocks APPS, LSP, IPA with expertise in test cases and bin’s generation. * Built VT (Virtual Tester) using Gate Level Models and EVCD to bin conversion environments. * Debugged Vmin/Fmax for CPU (ARM53, ARM57 and ARM72) on silicon and timing simulations. * Regressed VT simulations before silicon arrival and achieved First Time Right Vectors. * Translated production, AC/DC characterization, DPPM, RMA vectors for wafer sort and final testing. Gate Level Verification at SoC * Simulated SoC with Unit delay (no timing) and SDF for quality Tape out (28nm,14nm,10nm,7nm) * Analyzed and enhanced the functional GLS Test plan for SoC for improved coverage. * Built GATEIDs (Elaborated netlist model) using all IP netlists and cleaned up SDF issues. * Identified non-resettable FF/Latches, memories and fixed the initialisation and vectors. * Enhanced the functional GLS Test plan to cover changes, critical paths, ECO and resource optimisation. * Integrated IP Deliveries and test bench components to maintain stable simulation environment for verification * Discovered critical timing bugs in timing simulations which saved revision of the project. * Mentored teams on site on bringing up the Qualcomm GLS setup and created checklists.

* Coded the verification test-bench at module level to verify and increase the coverage. * Analyzed code and functional coverage and created the test-cases to cover the coverage holes. * Integrated the module to the chip and verified it at SoC level regressions in RTL and gate level.

* Programmed Instruction Set Simulator (High Level Language Model) and added functionalities for the * instructions. * Programmed the test cases in Assembly Language to test the Model itself. * Automated the testing of Simulator and debugged the results with Verilog processor model’s results. * Coded system Verilog assertions (SVA) to validate cache coherency in processor.

Student Worker at USC Book Store.Working as student reprensateive at Book Store. Helping in orders management for last 15 months