Juntae Park

- Designed and implemented NPU architecture features spanning core-level microarchitecture, multi-core cluster organization, multi-banked L2 SRAM hierarchy, and cluster-level interconnect in SystemVerilog RTL. - Performed workload-driven HW/SW co-design to explore compute, memory, and data-movement trade-offs for on-device AI, Physical AI, and VLA workloads. - Built Python-based reference models and verification utilities to generate test vectors, validate RTL behavior, and accelerate architecture-to-implementation iteration. - Analyzed state-of-the-art AI algorithms and model trends to identify compute, memory bandwidth, and dataflow bottlenecks, translating workload requirements into next-generation NPU hardware features.

Conducted research on approximation processing units as a visiting research intern.

Conducted undergraduate research at the Intelligent Robotics Lab under the supervision of Prof. Soo-Young Yi, Department of Electrical and Information Engineering.

- Specialized in AI Hardware Accelerator Design, focusing on FPGA-based neural network accelerators and system-level optimization for edge AI applications. - Conducted research at the Intelligent Digital Systems Lab (IDSL) under the supervision of Prof. Hyun Kim.

- Honored with the Presidential Award for Academic Excellence for outstanding academic performance - Received the Presidential Commendation for Meritorious Service for outstanding contributions to the university community - Awarded the Excellence Award at the Engineering Capstone Design Exhibition, presented by the University President - Ranked 1st in the Department of Electrical and Information Engineering Capstone Design Competition