Jungsuk Kim

Full Professor @ Gachon University

About

Ph.D. engineer who has design experiences in the areas of low-noise low-power preamplifier, low-offset comparator, switched-capacitor circuit, data converter (ADC/DAC), reference circuit, wireless data receiver, wireless power telemetry, RFID, CMOS sensor, DRAM, oscillator, biomedical ASIC, bioinstrument, DNA sequencer, implantable microelectronics

Country

South Korea

City

Seongnam

Industry

Consumer Electronics

Skill

Fundraising, New Business Development, Process Improvement, Healthcare, CMOS, IC, Circuit Design, Analog Circuit Design, Semiconductors, VLSI, ASIC, Low Power Design, Low Noise Design, Mixed Signal, ADC, DAC, DRAM, Wireless, RF circuits, RFID applications

Experience

Full Professor

Gachon University

2025-3 - Present · 1 yr 7 mos

Gyeonggi, South Korea

Dept. of Biomedical Engineering

Associate Professor

Gachon University

2019-10 - 2025-2 · 5 yrs 5 mos

Gyeonggi, South Korea

Assistant Professor

Gachon University

2014-2 - 2019-9 · 5 yrs 8 mos

Gyeonggi, South Korea

Chief Executive Officer

CELLiCO

2019-11 - Present · 6 yrs 11 mos

Gyeonggi, South Korea

☐ Wearable devices (AR glasses) ☐ Implantable devices (Retinal Implant) ☐ Healthcare devices (electroceutical)

Postdoctoral Scholar

University of California, Santa Cruz

2012-1 - 2013-8 · 1 yr 8 mos

California USA

☐ Ultralow-current (pA) measuring system for DNA sequencer (IBM 0.xn--13-m-nnd CMOS) • 0.9pARMS-noise CMOS potentiostat based on an integrator-differentiator architecture • Wideband transimpedance amplifier based on a bootstrapping technique • Time-Division Multiplexing system ☐ DNA Translocation speed control (US NIH-R21 Grant Award) • Novel dual-nanopore device and electronic control platform development

Graduate Researcher

University of California, Santa Cruz

2006-9 - 2011-12 · 5 yrs 4 mos

California USA

☐ Wireless data receiver for RFIDs and near body sensor networks (TI 0.xn--35-m-nnd CMOS) • 4Mbps non-coherent DPSK demodulator using a switched-capacitor circuit • 202pJ/bit 1.356Mbps RC-less ASK demodulator with adaptive thresholds • Low-power 2.5Mbps digital FSK demodulator with self-clocking recovery ☐ Integrated neural data acquisition system (TI 0.xn--35-m-nnd CMOS) • Fully-integrated self-biased 4.xn--9vrms-noise-6di 6.xn--7w-99b preamplifier • Low-offset comparator based on an input-offset storage technique • 6-bit 640Ks/sec successive-approximation ADC ☐ Neural stimulation current driving system (TSMC 0.xn--18-m-nnd HV CMOS) • 4-bit 100Ks/sec current-steering DAC • 500μA-scale 2.6%-mismatch push-pull current driver • 103.7dB-PSRR@242KHz beta-multiplier reference circuit ☐ Wireless power management for RFIDs and near body sensor networks • 52%-efficiency RF coil optimization technique using brute-force search algorithm • 2MHz-carrier high-efficiency Class-E power amplifier • Synchronous voltage rectifier and series low-dropout regulator

Teaching Assistant

University of California, Santa Cruz

2010-3 - 2010-6 · 4 mos

California USA

■ Course : Renewable energy sources (EE80J)

Cofounder, Consultant

Two Pore Guys, Inc.

2011-11 - 2013-8 · 1 yr 10 mos

California USA

Project Consultant for an integrated nanopore DNA sequencer design

Research Assistant

University of Southern California

2005-1 - 2006-5 · 1 yr 5 mos

California USA

☐ High-speed low-phase noise oscillator design using RF MEMS resonator • 5GHz, -117dBc@100KHz Colpitts oscillator using a FBAR resonator

Circuit Design Engineer

Samsung Electronics

2003-2 - 2004-4 · 1 yr 3 mos

Korea

☐ 90nm CMOS 512M DDR2 DRAM WD-version • Sensing amplifier, DC voltage regulator and charge pump

Education

University of California, Santa Cruz

Electrical Engineering

2006 - 2011 · 5 yrs

Advisor: Prof. Kenneth D. Pedrotti Co-advisor: Prof. William B. Dunbar Dissertation : Low-Power Low-Noise CMOS Integrated Circuits for Bioelectronic Applications