Joydeep Ray
Distinguished Engineer / GPU Architecture @ NVIDIA
About
GPGPU architect and Graphics hardware engineer. Previously, tablet/phone/notebook/desktop SoC architecture and micro-architecture, power-performance analysis and optimization (@Intel - last ~9 years). Experience in performance benchmarking, tuning and modeling, and micro-architecture design of multi-core Server chips (@AMD, IBM). Specialties: Memory controllers and memory sub-system architecture, cache coherency, optimizing performance for mW (phone/tablet), CPU performance benchmark design/development/analysis, Compiler Optimization.
United States
Folsom
Computer Hardware
Computer Architecture, Processors, SoC, Compilers, Compiler Optimization, Debugging, ASIC, Microprocessors, Architecture, X86, Microarchitecture, Application-Specific Integrated Circuits (ASIC), System on a Chip (SoC)
Experience
Distinguished Engineer / GPU Architecture
NVIDIA
Santa Clara County, California, United States
Graphics Architect
Intel
Sacramento County, California, United States
Lead GPU IP architect for compute pipeline. Played a key role in architecture, design and productization of Intel Arc GPUs and Intel Ponte Vechhio ML/HPC Accelerator.
SoC Architect
Intel
SoC architect for tablet/phones/notebook/desktop systems; Specializing in power/performance, memory interface and technologies, performance modeling, and on-die coherent interconnect. Apr 2014 - 2015: Integrated Sensor Hub architect. Focusing on power optimization, IP power modeling and new sensor-based technologies for Intel SoC. Jan 2013 - Apr 2014: Lead architect/micro-architect for a future Tablet/ULT/Notebook/Desktop SoC. Focused on coherent interconnect, innovative memory and storage technologies, innovative on-package memory and caching solutions. Led a team of ~6 architects. Sept 2011 - Dec 2012: Lead architect/micro-architect for Phone/Tablet SoC "North cluster" (CPU/GPU/Image processor coherent interconnect, shared cache, memory controllers, memory subsystem including I/O), Performance analysis and projection. Managed a team of ~6 architects. June 2008 - Dec 2011: Memory subsystem architect for Ivy Bridge CPU (3rd gen Core i3/i5/i7 - targeted for convertibles, notebook, ULT, desktop, UP server)
MTS Design Engineer
AMD
Austin, Texas Area
CPU performance architecture and modeling for multiple generation of AMD multi-core Server systems. Focusing on memory subsystem (memory controllers, DRAM technologies, DDR I/O), shared L3 cache and multi-core coherency. Also, tuned compilers, libraries and source code to extract best performance on AMD systems (targeting both standard benchmarks and real-world programs from developers).
Technical Representitive in CPU Sub-committee
Standard Performance Evaluation Corporation (SPEC)
Participated in the development of CPU2006, a industry-standard CPU benchmark suite.
Research Assistant
Carnegie Mellon University
Researcher in the Computer Architecture Lab (http://www.ece.cmu.edu/calcm/)
Design Engineer
IBM
Rochester, Minnesota Area
Performed RTL and functional verification responsibilities for disk controllers and server I/O controller ASICs.
Education
Carnegie Mellon University
Computer Engineering -- Computer Architecture
Indian Institute of Technology, Kharagpur
Electrical and Communication Engineering
Joydeep Ray's Contact Information
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