Jorge Marín

Jorge Marín

Associate Professor @ Pontificia Universidad Católica de Valparaíso

Country

-

City

Chile

Industry

Electrical & Electronic Manufacturing

Skill

Analog Circuit Design, CMOS, Matlab, Electronics, RF, English, LaTeX, Electrical Engineering, Mixed Signal, Programming

Experience

Pontificia Universidad Católica de Valparaíso

Associate Professor

Pontificia Universidad Católica de Valparaíso

LinkedIn
2025-11 - Present · 11 mos

Valparaiso Region, Chile

Advanced Center for Electrical and Electronic Engineering

Researcher

Advanced Center for Electrical and Electronic Engineering

LinkedIn
2023-12 - Present · 2 yrs 10 mos

Valparaiso Region, Chile

Advanced Center for Electrical and Electronic Engineering

Postdoctoral Research Fellow

Advanced Center for Electrical and Electronic Engineering

LinkedIn
2021-10 - 2024-3 · 2 yrs 6 mos

Valparaíso, Chile

Sony Depthsensing Solutions

Analog Designer

Sony Depthsensing Solutions

LinkedIn
2020-3 - 2021-9 · 1 yr 7 mos

Brussels, Brussels Region, Belgium

ICsense

Analg designer

ICsense

LinkedIn
2018-10 - 2020-2 · 1 yr 5 mos

Lovaina, Flandes, Bélgica

KU Leuven

Research Assistant

KU Leuven

LinkedIn
2012-9 - 2018-9 · 6 yrs 1 mo

Leuven, Belgium

Universidad de Chile

Project Engineer

Universidad de Chile

LinkedIn
2010-7 - 2010-9 · 3 mos

UAV for mining and geo-resources

Universidad de Chile

Teacher Assistant

Universidad de Chile

LinkedIn
2010-3 - 2010-7 · 5 mos

Teacher Assistant for EL652: Integrated Circuit Design Seminar course

Micomo

Project Engineer

Micomo

2010-5 - 2010-8 · 4 mos

Project engineer for BOTDR remote sensing system support

Universidad de los Andes (CL)

Lecturer

Universidad de los Andes (CL)

LinkedIn
2008-7 - 2010-7 · 2 yrs 1 mo

Lecturer, Analog Systems and Analog Design courses at Universidad de los Andes

Universidad de Chile

Teaching Assistant

Universidad de Chile

LinkedIn
2009-7 - 2009-10 · 4 mos

Teaching Assistant, EL3004: Analog Electronic Circuits

Synopsys Inc

Corporate Application Engineer

Synopsys Inc

LinkedIn
2009-6 - 2009-10 · 5 mos

Stress Testing to Clock Gating Low Power tool as Corporate Application Engineer for Power Compiler Group

Synopsys Inc

Engineer Intern (Master Thesis)

Synopsys Inc

LinkedIn
2007-12 - 2009-6 · 1 yr 7 mos

Development of parameter extraction strategies for industrial MOSFET compact models BSIM4 and PSP for TCAD Group Thesis document: https://repositorio.uchile.cl/tesis/uchile/2010/cf-marin_jn/html/index.html

Education

KU Leuven

KU Leuven

LinkedIn

Electrical and Electronics Engineering

2012 - 2016 · 4 yrs
KU Leuven

KU Leuven

LinkedIn

Electrical Engineering

2010 - 2012 · 2 yrs
Universidad de Chile

Universidad de Chile

LinkedIn

Integrated Circuits Design Mehtodologies

2007 - 2010 · 3 yrs
Universidad de Chile

Universidad de Chile

LinkedIn

Electronics

2001 - 2006 · 5 yrs

Jorge Marín's Contact Information

Email

******@***.com

Phone

(**) *** ****

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