John Busco
Director, Logic Design Implementation @ NVIDIA
About
Hands on experience with ASIC design implementation, solving problems and improving quality of results. Tool expert with an understanding of ASIC design. Experienced people manager. Specialties: ASIC EDA, logic synthesis, static timing analysis (STA), equivalence checking
United States
San Jose
Semiconductors
Electronics, Radio Frequency (RF) Engineering, Computer-Aided Engineering (CAE), Computer-Aided Design (CAD), Static Timing Analysis, ASIC, EDA, Perl, TCL, VLSI, Logic Synthesis, SoC, Low-power Design, Timing, Timing Closure, RTL design, Physical Design, Verilog, SystemVerilog, Semiconductors
Experience

Senior Manager, Design Implementation
Santa Clara, CA
Responsible for design implementation methodology and support used by all ASICs, ranging from low-power mobile systems on chip (SoC) to gigahertz-frequency multi-billion transistor flagship GPUs. EDA tool expert, problem solver and consultant. Manage a team supporting methodology, software development, and hands-on design closure.

ASIC Design Manager
· Managed design closure and ASIC vendor interaction for a multi-million gate 0.18 micron Switch ASIC. The ASIC achieved first-pass success. · Lead the team that developed a high-speed ASIC supporting 10 Gb protocols. · Floorplanning and I/O assignment on a pair of 0.10 micron ASICs.

Manager, System Level Integration
· Performed Logic Synthesis, Timing-Driven Design Planning and Timing Convergence on ASIC projects up to 3 million gates. · Technical strategist responsible for surveying EDA trends and initiating methodology advancement. Delivered Methodology Road Show to strategic customers. · Led a team of Methodology engineers to develop very successful capabilities in the Links-To-Layout and Design Planning area.
Education
John Busco's Contact Information
Phone
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