John Busco

John Busco

Director, Logic Design Implementation @ NVIDIA

About

Hands on experience with ASIC design implementation, solving problems and improving quality of results. Tool expert with an understanding of ASIC design. Experienced people manager. Specialties: ASIC EDA, logic synthesis, static timing analysis (STA), equivalence checking

Country

United States

City

San Jose

Industry

Semiconductors

Skill

Electronics, Radio Frequency (RF) Engineering, Computer-Aided Engineering (CAE), Computer-Aided Design (CAD), Static Timing Analysis, ASIC, EDA, Perl, TCL, VLSI, Logic Synthesis, SoC, Low-power Design, Timing, Timing Closure, RTL design, Physical Design, Verilog, SystemVerilog, Semiconductors

Experience

NVIDIA

Director, Logic Design Implementation

NVIDIA

LinkedIn
2017-10 - Present · 9 yrs

Santa Clara, California

NVIDIA

Senior Manager, Design Implementation

NVIDIA

LinkedIn
2002-12 - 2017-10 · 14 yrs 11 mos

Santa Clara, CA

Responsible for design implementation methodology and support used by all ASICs, ranging from low-power mobile systems on chip (SoC) to gigahertz-frequency multi-billion transistor flagship GPUs. EDA tool expert, problem solver and consultant. Manage a team supporting methodology, software development, and hands-on design closure.

Brocade

ASIC Design Manager

Brocade

LinkedIn
2000-7 - 2002-11 · 2 yrs 5 mos

· Managed design closure and ASIC vendor interaction for a multi-million gate 0.18 micron Switch ASIC. The ASIC achieved first-pass success. · Lead the team that developed a high-speed ASIC supporting 10 Gb protocols. · Floorplanning and I/O assignment on a pair of 0.10 micron ASICs.

Toshiba

Manager, System Level Integration

Toshiba

LinkedIn
1991-8 - 2000-7 · 9 yrs

· Performed Logic Synthesis, Timing-Driven Design Planning and Timing Convergence on ASIC projects up to 3 million gates. · Technical strategist responsible for surveying EDA trends and initiating methodology advancement. Delivered Methodology Road Show to strategic customers. · Led a team of Methodology engineers to develop very successful capabilities in the Links-To-Layout and Design Planning area.

IBM

ASIC/EDA Engineer

IBM

LinkedIn
1984 - 1991 · 7 yrs

ASIC designer, firmware (microcode) engineer, hardware bring-up, EDA methodology definition and development.

Education

Stanford University

Stanford University

LinkedIn

Electrical Engineering

Depth of study in computer software, with additional courses in Logic Design, Design for Test, and VLSI.

University of California, Berkeley

University of California, Berkeley

LinkedIn

Electrical Engineering and Computer Science

Graduated with High Honors.

University of California, Santa Cruz

University of California, Santa Cruz

LinkedIn

Engineering

John Busco's Contact Information

Email

******@***.com

Phone

(**) *** ****

Find the Right Leads
Find Verified Contact Data

Try with: Jensen Huang @ nvidia.com Click to autofill
LeadContact awards, five-star ratings, and GDPR compliance badges

What LeadContact does well

Find verified emails, phone numbers, and decision-makers with 98% accuracy.

Find Leads

Find Leads

Find the right people by company, role, industry, location, and more.

925M+ professional profiles

Find Leads
Find Emails

Find Emails

Access verified email addresses for your target contacts.

657M+ emails

Find Emails
Find Phone Numbers

Find Phone Numbers

Get cross-validated phone data from multiple top sources.

239M+ phone numbers

Find Phone Numbers

More Accurate. Lower Cost.

Find contact data in 1 tool with 98% accuracy

LeadContact integrates leading enrichment tools to deliver more accurate contact data—without paying for each one.

LeadContact Logo
Competitor Tools

All these = $289 per month

Great conversations start with the right contact.

It’s time to find yours.