jigar desai

fpga engineer

About

Seasoned engineer with 3+ years of experience in FPGA development. Expertise in RTL coding, synthesis, placement, optimization, timing closure, mixed-signal modeling, scripting and PCB board debugging.

Country

united states

City

san jose

Industry

mechanical or industrial engineering

Skill

matlab, vhdl, verilog, c, c++, modelsim, system verilog, perl, altera quartus, nios ii, cadence virtuoso, vcs, amba apb, amba ahb, nc verilog, cadence virtuoso xl, c++ language, unix, vivado, pci standards, xilinx project navigator 6.1, eagle pcb, edwin, autocad, visual basic

Experience

fpga engineer

sodick america corporation

2016-6 - Present · 10 yrs 4 mos

* Expertise in making platform independent and modular RTL designs * RTL designs for various external peripherals like PLL, EEPROM, ADC, DAC, host processors * Experienced with complex protocols such as DDR3, 1G/10G Ethernet, AXI-4 Bus and BFMs * Optimize algorithms, propose design architectures and integrate designs at system level * Well acquainted with Hardware Co-Simulation using System Generator and Simulink * Assist PCB designers in schematic validation, board bring-up and hardware debugging * Experience with soft-core (Micro-Blaze) and hard-core(Zynq) processors in FPGAs * Lead 2 interns, assertive, self-starter with excellent organizational skills using JIRA

fpga design engineer

semplus corp

2015-2 - 2016-6 · 1 yr 5 mos

* Implementing the hardware module for 3rd Generation Touch driver, using SoC Xilinx (Virtex- 7) and Altera FPGA (Cyclone Family). In particular, responsibility also includes:- * 1. Implementing of the front-end with the acquisition board, communication (e.g I2C, UART, USB) * with a host processor defining a specific protocol and touch algorithm hard-wiring. * 2. Demonstrating fully conversant experience with functional simulation using ModelSim. * 3. Experiencing with digital systems using micro-controller and FPGA based SoC. * 4. Implementing Communication with DDR3/ DDR2. * 5. Experience with System on Chip Integration and verification. * 6. Work with algorithm / Data Analysis using Matlab / Octave. * 7. Knowledge and ability to use lab equipment - Oscilloscope, Spectrum Analyzer, JTAG ICE tools, etc., for debugging and analysis of hardware. * 8. Good documentation skills, including maintaining information on Wiki, Git.

graduate assistant

san jose state university

2014-1 - 2014-12 · 1 yr

Graduate Assistant for the course Semiconductor Devices I under the guidance of Professor Javad Zoorofchi. Responsibilities includes to assist and solve the doubts of graduate students for semiconductor devices such as Diodes, BJTs, and MOSFETs also conducting labs to demonstrate the device characteristics on SPICE.

Education

san jose state university

2013-1 - 2015-1 · 2 yrs 1 mo

university of mumbai

electronics engineering

2008-1 - 2012-1 · 4 yrs 1 mo

Activities and Societies: * Gave a Seminar on JTAG to First Year Engineering Students. * Workshop on PCB Layout Designing. * Member Of IEEE and The Electronic Engineers Students Association (EESA).