Evan Jiang

Evan Jiang

Analog Design Engineer @ AMD

Country

United States

City

Pittsburgh

Industry

Consumer Electronics

Skill

Cadence Spectre, ADE, Cadence Virtuoso, Cadence Software, Cadence Virtuoso Layout Editor, Cadence, Assura, Calibre, Process design kit, Layout Versus Schematic (LVS), Design Rule Checking (DRC), Layout Design, Very-Large-Scale Integration (VLSI), EDA, Silvaco, Semiconductor Process, Semiconductor Lasers, Compound Semiconductors, Semiconductor Fabrication, Agile Project Management

Experience

AMD

Analog Design Engineer

AMD

LinkedIn
2026-1 - Present · 9 mos

Boxborough, MA

Draper

Physical Silicon Design Intern

Draper

LinkedIn
2025-5 - 2025-8 · 4 mos

Cambridge, Massachusetts, United States

- Designed IC layouts for various radiation hardened PLL circuit components, ensuring layouts are PDK clean - Modified circuit schematics for enhanced radiation mitigation capabilities - Performed schematic and extracted simulations to verify functionality and performance of devices

Northrop Grumman

PDK Engineering Intern

Northrop Grumman

LinkedIn
2024-6 - 2024-8 · 3 mos

Washington DC-Baltimore Area

- Designed and adjusted layouts for various experimental superconducting chips using Cadence Virtuoso. - Debugged and developed to existing DRC and LVS rulesets to ensure for multiple microprocessor technologies. - Migrated and converted DRC and LVS rulesets from the Cadence-Assura run language to the Mentor-Calibre language. - Created multiple QA test cases in Cadence Virtuoso to certify the proper functionality of the written DRC ruleset files.

Northrop Grumman

Hardware Engineering Intern

Northrop Grumman

LinkedIn
2023-5 - 2023-8 · 4 mos

Washington DC-Baltimore Area

-Collaborated with physicists to create an automation framework for instruments used for testing quantum computers. - Used BASH to create a script to automate remote communication of over 30 instruments to verify status and connection. - Utilized SCPI commands and developed instrument drivers using Python. - Performed loopback testing on several instruments to ensure desired functionality. - Increased scalability and useability of instrument drivers

Education

Carnegie Mellon University

Carnegie Mellon University

LinkedIn

Electrical and Computer Engineering

2025-8 - 2027-5 · 1 yr 10 mos
The Ohio State University

The Ohio State University

LinkedIn

Electrical and Computer Engineering

2021-8 - 2025-5 · 3 yrs 10 mos

Evan Jiang's Contact Information

Email

******@***.com

Phone

(**) *** ****

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