Jia Z.

Jia Z.

Manager AI Accelerator Customer Engineering @ Intel

About

Engineering Manager leading AI Accelerator Customer Engineering team, where we enable, validate, and launch AI accelerator platforms with partners and OEMs. I thrive on solving complex challenges, aligning cross-functional teams, and turning ambiguity into scalable solutions that accelerate time-to-market.

Country

-

City

United States

Industry

Semiconductors

Skill

GPU, Solution Architecture Collaboration, Co-Validation with OEMs & Partners, AI Accelerator, Server Platform Validation, Co-validation, Engineering Team Leadership, Customer Relationship Management, Analytical Skills, Stakeholder Management, Stakeholder Engagement, Team Leadership, Customer Service, Systems Engineering, Computer System Validation, Project Planning, Process Improvement, Shell Scripting, Technical Program Management, Cross-functional Collaborations

Experience

Intel

Manager AI Accelerator Customer Engineering

Intel

LinkedIn
2024-8 - Present · 2 yrs 2 mos

Hillsboro, Oregon, United States

Intel

Senior Systems and Hardware Enabling Engineer

Intel

LinkedIn
2021-8 - 2024-8 · 3 yrs 1 mo

Hillsboro, Oregon, United States

• Managed the establishment and launch of the Datacenter GPU Verified Library program to verify OEM/ODM systems and scale high-performance GPU and AI Accelerators across the organization. Led the platform/system level validation team to develop hardware platform functional testing and automated software performance tests. Support OEM/ODM system enabling and verification. • Recipient of the 2023 Q4 Data Center AI Solution Department Recognition Award for delivering and launching the Intel GPU-Ready Verification Program for the first time.

Intel

System-on-Chip Design Engineer

Intel

LinkedIn
2019-1 - 2021-8 · 2 yrs 8 mos

Hillsboro, Oregon

• Led SerDes IP quality validation and collaborated with an external IP provider. Developed automation scripts for DFT verification and ensured HVM pattern suite readiness. Conducted scan and MBIST insertion, delivered DFT-inserted netlists ahead of schedule, and generated test patterns for regression validation. Owned FEC flow and methodology across all design partitions, leading memory BIST validation efforts. Executed and debugged SystemVerilog/SVF test benches for post-DFT designs.

Intel

Logic Design Engineer Intern

Intel

LinkedIn
2018-6 - 2018-12 · 7 mos

Hillsboro, Oregon

• Created Perl scripts to automated ATGP Serial Vector Format testing and reduced MBIST verification time by 60% • Performed DFX executions, formal equivalence checking, and MBIST validation on a successful 5G ASIC • Collaborated with design engineers to resolve memory array design and verification issues • Awarded by the business department (DAR) with the design of custom RTL modules to integrate into the verification model to get the design process out of the critical path

Leviton

Software Engineer Intern

Leviton

LinkedIn
2017-12 - 2018-6 · 7 mos

Portland, Oregon Area

• Developed an Android mobile app to run extensive automated testing on wireless light switches using Java • Built a desktop GUI as an engineering testing tool to test Wi-Fi smart home devices using Python

Portland State University

STEM Mentor

Portland State University

LinkedIn
2014-9 - 2015-3 · 7 mos

Portland, Oregon Area

• Led students to develop engineering prototypes through projects to increase the understanding of the engineering process • Promoted diversified student body in the STEM field to create an inclusive environment

Education

Portland State University

Portland State University

LinkedIn
Portland State University

Portland State University

LinkedIn
Portland State University

Portland State University

LinkedIn

General Science, Minor in Chemistry & Biology

Jia Z.'s Contact Information

Email

******@***.com

Phone

(**) *** ****

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