JIA JET HON
DFT Engineer @ Oppstar Berhad
Malaysia
Seremban
Semiconductors
tessent, Verilog, DFT, Verdi, Field-Programmable Gate Arrays (FPGA), ATE, Test Planning, MATLAB, Debugging skill, C++, Problem Solving
Experience
DFT Engineer
Oppstar Berhad
Federal Territory of Kuala Lumpur, Malaysia
-MBIST Soft IP design and Validation on Dual Port Memory -IO Loopback Validation using Soft IP as pattern generator and comparator -Boundary Scan Validation using bsdl-only flow
Test Development Engineer Intern
JF Technology Berhad
Petaling Jaya, Selangor, Malaysia
-IC Testing(DC parametric&Funtionality) -Test Plan and Test Program Development(ETS) -ATE(Teradyne ETS-364) -Schematic&PCB Design for Dummy DUT
Education
University of Malaya
Electrical Engineering
Malacca Matriculation College
Computer Science
JIA JET HON's Contact Information
Phone
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