Jerry Yu

 Served as primary interface between U.S R&D and Foundry supplier for VCSEL program.  Drove process development of 1550 nm /1060 nm VCSEL Flip-chip laser processes; executed MPI milestones (TO, DOE, Corner, Qual) to ensure a smooth transition to MP. Successfully completed product customer sampling and achieved a pilot run capacity of 4k units/month.  Executed process development and technical feasibility assessment for next-generation 1550 nm / 1060 nm wide-tunable-range VCSELs, successfully delivering prototypes.  Collaborated cross-functionally with Engineering and Packaging teams to resolve process and quality issues during new product development.  Managed Contract Manufacturing (CM), including project planning and schedule control

 Process development for Tunable VCSELs, overcoming significant etching challenges associated with Grating structure. Stabilized Critical Dimension (CD) and depth control by implementing dry etching processes, enhancing device characteristics.  Executed DOE (Design of Experiments) planning and analysis, performing failure mode identification and improvement measures to support continuous process optimization and yield enhancement.  Managed VCSEL chip mask design and layout.

 Led a cross-functional team of 2 engineers and 4 operators to manage OEM projects through the full product lifecycle, from initial sampling to mass production. Successfully converted OEM collaborations into official production contracts  The evaluation and deployment of chip processing equipment for Edge Emitting Lasers (EEL). Led the end-to-end establishment of the CMP (Chemical Mechanical Planarization) station, managing facility requirements, equipment installation, and performance qualification (PQ). Successfully enhanced wafer thickness control.  Engineers training, significantly enhancing overall process execution capabilities and operational efficiency.

 Established an in-house DFB wafer process for rapid performance testing of proprietary Epi Wafers. ---Cutting feedback time to the Epi team to under one month and boosting design efficiency. ---Provided Technical Data Sheets support of Epi wafer to enhance customer confidence in Epi Wafer stability and assist the sales team with technical issue resolution.  Managed the design and layout of semiconductor chip masks (mask layout)  Developed and implemented IPQC and SPC monitoring systems.  Planned and executed Design of Experiments (DOE) and failure mode analysis to optimize process parameters and enhance product reliability.

 Epitaxial Wafer Mass Production: Responsible for recipe editing, process troubleshooting, cost-reduction projects, and yield enhancement.  R&D Support: Assisted the R&D team in completing testing and evaluation for new product samples.