Jeevan N V

-> Led ASIC design & verification (RTL, UVM, GLS, CDC) for high-performance SoCs with mixed signal interfaces, delivered 2 successful tapeouts by driving RTL and verification closure across datapaths and control logic. -> Designed RTL datapaths for low-latency digital filters and calibration engines (RC trim, PLL calibration, offset correction) significantly improving signal precision and reducing latency. Developed digital algorithmic modules (Polynomial solver, auto-calibration sequencing, frequency-monitoring, reset controller) to enhance efficiency. -> Developed a scalable UVM verification environment for digital IPs (SPI, Fuse, SRAM, CSRs) and authored comprehensive test and coverage suites, achieving 95% functional coverage and resolving CDC and GLS issues. -> Architected golden reference models for datapath and calibration algorithms in MATLAB/Python, guiding RTL micro-architecture and benchmarking performance to accelerate verification cycles.

-> Developed RTL for a Non-Volatile Memory (NVM) controller with single-bit ECC, ensuring data integrity through protocol handling and parity logic. -> Automated post-silicon debug with Python and Verisium, creating CocoTb-based testbench infrastructure, improving validation efficiency and reducing debug time. Increased coverage convergence by 30% and accelerated closure. -> Performed power analysis on the MASH fractional-N divider using Cadence Joules, optimizing RTL design to reduce power consumption and enhance system efficiency.

-> Streamlined SystemVerilog testbench coverage extraction with Python and Cadence vManager, optimizing digital regression speed and coverage reporting efficiency, resulting in significant processing time reduction. -> Linked UVM test environments with automated coverage reporting, enhancing debug visibility and reducing manual effort across Verilog-based digital architecture regressions.

IoT/Embedded Systems Prototyped a microwave assisted pyrolysis system for plastic waste treatment, using COMSOL Multi physics to model coupled electromagnetic thermal behavior and optimize heat distribution. Implemented embedded control logic with integrated thermal sensing for real-time regulation, achieving an 18% improvement in energy efficiency.

Coursework : - CSE 240A : Computer Architecture - ECE 260A : VLSI Digital System Algorithms and Architectures - ECE 284 : Low-Power VLSI Design for ML Accelerators (RTL) - ECE 260B : VLSI Integrated Circuits and System Design - ECE 213 : Parallel Computing