Jayesh Gharat

Jayesh Gharat

GPU partition design engineer @ Apple

About

Master of science in Electrical engineering

Country

United States

City

Austin

Industry

Electrical & Electronic Manufacturing

Skill

Verilog, Matlab, c, C++, perl, Microsoft Excel, Debugging, HTML, SQL, C, Device Drivers, Windows, Linux, Microsoft Office, Java, Microcontrollers, Embedded Systems, Perl

Experience

Apple

GPU partition design engineer

Apple

LinkedIn
2022-2 - Present · 4 yrs 8 mos

Austin, Texas, United States

Intel

SOC Physical design engineer

Intel

LinkedIn
2017-1 - 2022-3 · 5 yrs 3 mos

Folsom, United states

• RLS designer of logic blocks in OOO Cluster for Intel’s 7nm CPU for next generation client and server products. As a designer executed design from RTL2GDSII flow. • Worked on all aspects of physical design implementation floor planning, place and route, clock tree synthesis, timing optimization. • Responsible for converging timing, beat up power goals, meet RV targets. • Worked on a complete project from TR phase to tape in on 10nm process node. • Responsibilities include physical design activities such as placement, routing, convergence of the design with respect to timing, power, EM IR, noise using Intel proprietary tools. • Responsible for designing semi-custom CMOS circuits, translating RTL to circuit schematics. • Performed formal equivalence verification of gate level circuit to ensure match to RTL. • Worked on high complex datapath fubs(Structured Design) to optimize circuit behavior to meet performance, timing, power targets, quality metrics. • Good understanding of Out of Order CPU Design worked with RTLers on backend feasibility studies and their impact on timing and power. • Design for Testability reviewer for OOO cluster. Good understanding of stuck at and at speed coverage concepts.

Intel

Component Design Engineer intern

Intel

LinkedIn
2016-1 - 2016-12 · 1 yr

Folsom, United states

• As a physical design intern worked on logic blocks in FE & OOO Cluster for Intel’s 14nm CPU products • Worked on VLSI circuit design, schematic entry, static timing analysis, layout optimization • Responsible on logic implementation and timing convergence for high-speed low power multi-GHz circuits

Kalyani Technologies Process and Power Electronics

Junior Trainee Engineer in embedded systems

Kalyani Technologies Process and Power Electronics

2013-7 - 2014-7 · 1 yr 1 mo

Pune Area, India

Responsibilities: • Develop device drivers to interface various peripheral hardware resources such as EEPROM, RTC on I2C bus. Develop code to support on-board analog / digital input channels, schedule blocks and auto detection of hardware resources configured by user. • Use of logic analyzers, DMM, Oscilloscopes for hardware debugging and hardware bring up. Projects: • Differential pressure measurement made for Mahindra and Mahindra Pvt Ltd. • Smart controller: This is a user terminal for interfacing with wireless SCADA based on 2.4GHz Zigbee module • Scanner Interface: Reads serial data from external devices such as a bar code scanner & transfers this to SCADA over RS485 MODBUS. • Tourniquet: Pressure or vacuum controller for medical use. Pressure/vacuum is settable with the up/down keys along with cycle time. The unit controls pressure pump & solenoid to control the pressure for the set time.

Education

California State University-Sacramento

California State University-Sacramento

LinkedIn

Electrical and Electronics Engineering

2014 - 2016 · 2 yrs

Jayesh Gharat's Contact Information

Email

******@***.com

Phone

(**) *** ****

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