Jay Hanbaba

Lead the system content and design validation team responsible for delivering verified and stable content to system high volume manufacturing test program team. The team owns delivery of the end 2 end IP content from test requirement, 1st silicon power on, SOC/Core content debug/characterization to eventual product release qualification (PRQ) of Intel Oregon client products based on Intel 4, 18A & future process nodes.

Senior staff engineer responsible for the development and piloting of new client CPU test and manufacturing solutions. Executed multiple test readiness projects, defining technical roadmaps and strategies, collaborating with internal engineering teams and external module partners to pilot new test methodologies for the latest generation client products. Led the validation, and deployment of an automated, scalable, and converged processor thermal solution for a high volume, disaggregated client processor by leading a cross-organizational team.; achieved thermal mitigation result for top SKU bin split units, significantly reducing multi-pass to single-pass test time for high-powered multi-core array and functional tests.

Led a team of application engineers responsible for post-silicon high-volume test methods deployment and support across all client and server product teams utilizing Azure infrastructure. Provided technical guidance, leadership and vision, resolving difficult silicon sightings and delivering solutions exceeding product team expectations. Built a technically competent and resilient team through performance management and technical mentoring.

Managed a team of software engineers through developing and supporting new manufacturing test capabilities, influencing stakeholders to align on solutions to complex engineering challenges. Demonstrated leadership in driving cross-organizational collaboration.

Developed post-silicon test programs validating an FPGA-based tester that accounts for over 90% of Intel silicon testing today through close collaboration with design, system software, and manufacturing groups; promoted to senior engineer for significant contributions. Conducted hardware and software validation/debug of critical components of the automated test equipment (ATE). Utilized Python software development skills to root cause, provide workaround, and mitigate hardware and API issues.

SRAM memory test chip test program development & silicon debug for qualification of new process technology at Intel Advanced Design group.

Converged core development group.

Sort test technology development.

Fab process engineer.

ECE540: System-on-chip Design with Programmable logic ECE510: Post-silicon Functional Validation Develop and teach graduate courses related to programmable logic and post-silicon validation at Maseeh College of Engineering & Computer Science.

Planed, organized and executed launch events, tech-talks and other activities that involved Microsoft at the University of Washington.

Sort test program development intern.