Jason Tsai

Senior Application Specialist @ Onto Innovation

About

5 years to finish bachelor and master degree of chemical engineer department of NCKU. 2 years of process engineer in litho department of tsmc F15A for maintaining product yield and tool performance. 10+ years of application engineer of Onto Innovation for metrology tool (OCD) performance optimization and metrology recipes set up for new tech inline measurements at customer site, including software test, trouble shooting inline problems, machine learning and RCWA model recipe set up.

Country

Taiwan

City

Taichung City

Industry

Semiconductors

Skill

Machine learning, Frontend process of semiconductor, White Light Interferometry, Backend Process, TSV, OCD Metrology, 英文, 資料分析, 工程, 品質管理, 半導體, OCD, 六西格玛

Experience

Senior Application Specialist

Onto Innovation

2022-11 - Present · 3 yrs 11 mos

台灣 Taiwan 新竹市

Senior Application Engineer

Onto Innovation

2020-4 - Present · 6 yrs 6 mos

台灣 Taichung City 臺中市

-Machine learning and RCWA model recipes build up for tsmc R&D cutting edge tech transferring to Fab. -Collaborate with service team solving inline issues at customer site. -Build up series of thing film recipes in tsmc F12 fab for recipes transferring from competitor tools. -Thing film recipes BKM set up. -New software qualification and testing for new product introducing.

Application Engineer

Onto Innovation

2016-11 - 2020-4 · 3 yrs 6 mos

台灣臺中市

-New tool installation and quality control for OCD Metrology tools at customer sites. -RCWA models set up for the first tool qualified by Maxchip in IGBT process measurements and set up series of RCWA models in the following year. -Support new tool installation for matching project of VNAND process at Intel fab.

Application Engineer

Onto Innovation

2015-1 - 2016-11 · 1 yr 11 mos

台灣臺南市

-New tools of Unifire (White Light Interferometry) installation in tsmc bumping fab and F14A for backend and TSV process measurements. -Sustained tool performance and set up series of recipes for the various applications for customers, such as TSV, erosion / dishing, warpage at frontend process and bump height, protrusion and InFo at backend process.

Process Engineer

TSMC

2012-9 - 2015-1 · 2 yrs 5 mos

Taichung

2012/9-2015/1 Process Engineer of nano lithography (tsmc F15A) - New tools installation for mass production. - Inline wafer quality maintain through various monitoring system, such as CD / Overlay and defect inspection. - BKM recipe set up for within wafer CD optimization. - Assigned to be the Fab RMS sponsor of F15A. By regularly meeting with RMS sponsors from different department of F15A, F15A was the only Fab that reached 100% OI grouping rate among tsmc other fabs.