Jarvis Hung

Application Engineer @ SPTS Technologies Ltd, a KLA Company

About

My name is Jarvis Hung who works as R&D engineer in ITRI currently. My career starts form Oxfords Instruments which is vendor of front company. I played the role of process in Oxford Instruments which handled the PECVD & dry etching projects in that period. Moreover, the projects are including PSS etching and passivation thin film deposition in TSMC LED Lab, core layer deposition of wave guide in Sanan, dry clean cycle time in Epistar and nPSS dry etching in Asahi. In ITRI, I am also a R&D engineer who handle research of the MEMS display with Qualcomm. Furthermore, I do the structure research and fix the issue from the Qualcomm. In technical field, I have experience to do many kinds experiment for pattern with thin film deposition PECVD/PVD and dry etching ICP/RIE. I am good at study the paper that I want to resolve the issue and communicate with people in these kinds of technology, I can utilize my knowledge about the process science and make contribution to the development of company.

Country

Taiwan

City

Hsinchu City

Industry

Semiconductors

Skill

R&D, MEMS engineer, LED Lighting Systems, Thin Films, Plasma Physics, JMP, DOE

Experience

Application Engineer

SPTS Technologies Ltd, a KLA Company

2015-9 - Present · 11 yrs 1 mo

Hsinchu County/City, Taiwan

Responsibility  Handle many accounts within high technology industry as TSMC, PTI, Chipbound, Win-Semi, San-An and unicompound.  Handle process issues and requests from customer site.  Lead and own process projects about CVD and PVD tools.  Co-work with customer to develop the process for applications. Major achievement  Release tools to customer and get acceptance on time.  Always optimize the process to achieve customer’s request.  Promoting our tools for new application to R&D from customer.  Issue the process startup qualification (power point file) to customers as the final process startup report.  Resolve all the process related issues during the process startup period.  Assist customers to develop the new PVD process applications.  Co-work with UK lab team for CVD demo report.

R&D Engineer

Industrial Technology Research Institute (ITRI)(工業技術研究院, 工研院)

2013-4 - Present · 13 yrs 6 mos

Hsinchu County/City, Taiwan

Project owner managing and co-working with Qualcomm/sharp MEMS department. 1. CVD/PVD tools owner managing process control and troubleshooting with different kinds of film. 2. ICP/RIE tools owner responsible for of dry etching process with film in combination. 3. Responsible for CVD tools developments including tool qualification, wafer handling upgrades and preventative maintenance scheduling.

Process Engineer

Oxford Instruments plc

2011-4 - 2013-4 · 2 yrs 1 mo

Hsinchu County/City, Taiwan

Project/CVD tools owner responsible for troubleshooting, wafer/sample managing, tools development. 1. Handle TSMC LED Lab, Sanan & Epistar projects development with PECVD. SiO2 film quality thin film for low etching rate in right stress by BOE. SiN passivation thin film for LED & power device with low stress. SiO2 doped with Ge in right reflective & good stress in waveguide device. 2. Handle Asahi, Epistar & Sanan projects development with ICP/RIE. PSS/nPSS of LED dry etching. GaN mesa etching. SiC of power device etching.

Research Assistant

National Tsing Hua University

2008-10 - 2011-3 · 2 yrs 6 mos

Taipei City, Taiwan

1. Multiple light sources of various coherences, wavelengths, and pulse durations to achieve coherent control or selective control in a non-equilibrium system and the growth or transition of materials. 2. High density laser science