Jane Wang

Focused on drive development and factory process, reliability features development and implementation, product verification and validation. • Launched new products. Initiated the electrical design, monitored the process, optimized the design, analyzed production data and bench worked on drives. Defined/modified process parameters, optimized the process and drive parameters in reaching yield and transferred the process/parameter to other function groups. Successfully developed two products. • Built and optimized channel model with ANOVA regression tool. Tested and optimized this new dual reader mixed signal channel on bench. Built model based on data in finding better optimization methods. Also worked on the FPGA prototype of the MSMR channel in predicting dual reader gains. Successfully estimated and secured the gains for the new channel. • Partnered cross-functionally to design and develop reliability features in catching marginal products, reducing field failure rate and keeping factory yield. The features were implemented in drives and in factory process.

Focused on drive subsystem characterization. Tests and test system design on both hardware and software. • Upgraded spin stand test system to LXI system. Programmed higher level API and tests to users. Maintained the test system on daily basis. Testers and tests were used daily for servo format evaluation. • Found key factors on spin stand for head and media design DOE; optimized the design parameters and further improved the product quality. • Explored analytical and experimental methods to measure/estimate the servo linearity, linear and track density, servo pattern quality and thermal stability. Implemented spin stand tests and predicted numerous products servo linear and track density, linearity. Supported Seagate 5 year warranty.

• Investigated and evaluated architectures for high speed and programmable VCO in PLL circuit. Performed VCO single band phase noise analysis with Cadence. Simulated, verified and characterized dithering PLL with Hspice • Performed metal layer noise coupling analysis in verifying the shielding mash effect. • Applied I/O cells and internal cells VHDL and Verilog model verification. Provided troubleshooting support to customers. • Provided verification automation. Maintained and upgraded internal tools.