Jaina Patel

Senior GPU Design Engineer @ Qualcomm

About

Silicon Design Engineer with 4+ years of experience in digital logic design and verification. Proficient in all facets of the digital design flow, including architecture specification, RTL implementation, Verification, DFT, Synthesis, CDC. Proven expertise in micro-architecture development, collaboration with cross-functional teams and support for hardware engineering activities. Technical Skills ● HDL: Verilog, System Verilog, UVM ● Programming Languages: C, Python ● Scripting Languages: Perl, Shell ● Proprietary Simulator: Synopsys VCS, Vivado, Modelsim, Questasim, Quartus, Design Compiler, IC compiler I, Cadence Virtuoso, Encounter, Cadence Xcelium, Spyglass, VC Spyglass, TetraMax

Country

United States

City

Seattle

Industry

Semiconductors

Skill

H.264, H.265, Verification (System Verilog, UVM), Functional and Code coverage, Ethernet PHY, Perl scripting, Synthesis and Static Timing Analysis , ATPG/DFT, SoC Packaging, Post-Silicon Validation, FPGA prototyping, MATLAB , RTL design (Verilog), Verification (System Verilog), CDC, RDC, Lint, Functional Coverage, Verilog, RTL Coding, Xilinx ISE, ARM Architecture

Experience

Senior GPU Design Engineer

Qualcomm

2025-6 - Present · 1 yr 4 mos

Santa Clara, California, United States

Adreno GPU team

Senior Silicon Design Engineer

AMD

2022-5 - 2025-6 · 3 yrs 2 mos

Markham, Ontario, Canada

Video Codec team

ASIC Digital Design Engineer, II

Synopsys Inc

2021-4 - 2022-5 · 1 yr 2 mos

Mississauga, Ontario, Canada

56G Ethernet IP

ASIC Digital Design Engineer, I

Synopsys Inc

2020-10 - 2021-4 · 7 mos

Mississauga, Ontario, Canada

Digital IC Design Engineer

Marvell Technology

2020-6 - 2020-8 · 3 mos

Toronto, Ontario, Canada

Research Intern

University of Toronto

2019-5 - 2020-5 · 1 yr 1 mo

Toronto, Canada Area

● Designing and deploying FPGA based Test Framework for performance characterization of Analog Front End of a fully-implantable IC designed to monitor electrochemical signals in the human body. ● The test framework is generic- which ensures that only the digital logic pertaining to the architecture of AFE needs to be modified for future generation ASICs while the rest of the system can remain same. ● Created and Packaged Custom IPs in Vivado and integrated on Nexys Video FPGA board to program and control the IC. ● Implemented ARM cortex M3 processor on Xilinx Arty-7 FPGA to study its resource and power utilization and feasibility for on-chip implementation. ● Designed testbench for 4K custom SRAM in PULPino RISCV open-source core implemented on 65nm chip.

Graduate Teaching Assistant

University of Toronto

2019-1 - 2020-4 · 1 yr 4 mos

Toronto, Canada Area

● Courses: Computer Organization (CSC 258), Digital Systems (ECE 241) ● Tasks: Tutorials on Verilog- HDL, Lab Sessions on DE1-SoC board, Conduct office hours

Research Intern

Dhirubhai Ambani University

2018-4 - 2018-7 · 4 mos

Gandhinagar

● Designed and synthesized a 5-Stage Pipelining Architecture for RISC-32 bit ISA (Verilog RTL), supporting Hazard Detection and Control Unit to avoid Data Hazards, a 2-bit Branch Predictor to avoid Control Hazards and separated Data Memory and Instruction Memory to avoid Structural Hazards. ● Synthesized the design using Synopsys Design Compiler (with necessary STA analysis). Supported Instructions: Arithmetic, Logical, and Branching.

Education

University of Toronto

Computer Engineering

2018 - 2020 · 2 yrs

Area of Specialization: ASIC Digital Design ● ECE 1762: Algorithms and Data Structure ● ECE 552: Computer Architecture ● ECE 1388: VLSI Design Methodologies ● ECE 1718: Hardware Accelerated Digital Systems ● ECE 1755: Parallel Computer Architecture and Programming ● ECE 1782: Programming Massively Parallel Multiprocessors and Heterogeneous Systems ● ECE 1756: Reconfigurable Computing and FPGA Architecture ● ECE 2500: Master's Project (Supervisor- Prof. Roman Genov)