Hyung Keun Park

◎ Summary OPC engineer specializing in the process development of logic device. Experienced with all stages of the development cycle for 3nm middle-of-line layers, from the OPC modeling to the mask tape out and revision. Had working familiarity with Linux OS, and experienced with TCL, Perl, and Python scripting. Well-versed in OPC design tools including Calibre and Tachyon. Strong background in material science and engineering. ◎ Skill Highlights - OPC modeling - OPC set-up & recipe tuning - Process margin analysis - SVRF (DRC), TCL scripting - Technical writing - Finite element analysis ◎ Experience Logic OPC staff engineer @ Samsung Semiconductor Research Center, Korea (2021 ~ ) - Improve lithography process margins through RET technology development and application. - Carry out the entire process of OPC performance to achieve the CD level required for 3nm EUV layers. - Devise OPC modeling techniques and development strategies to ensure accurate CD targeting and stable process margins. - Analyzes differences between wafer process and simulation and improves OPC consistency & coverage through preliminary verification of random patterns. - Cooperate with the product teams to monitor the product defects and yield, and discuss the direction of mask revision by OPC. ◎ Project / Interest - Contour modeling - CLOPC - EUV contact layer OPC modeling - Optimization process