How Ern Tan

Senior Product Development Engineer @ Intel

About

Senior Product Development Engineer with 9+ years of experience in post-silicon validation, specializing in MBIST test development, Functional DDR testing, and high-volume manufacturing (HVM) enablement at Intel. 🔹 Expert in root cause analysis, defect screening, and yield improvement strategies 🔹 Led Functional DDR testing initiatives, aligning ATE results with simulation to meet DPM goals 🔹 Developed and optimized test automation (Python, Shell, C#), boosting debugging and throughput 🔹 Proven success in driving PRQ readiness and scalable ATE solutions through cross-functional collaboration Passionate about building robust, data-driven test infrastructures and driving continuous improvement in silicon validation and product quality.

Country

Malaysia

City

Penang

Industry

Semiconductors

Skill

MBIST (Memory Built-In Self-Test), Post-Silicon Validation, Functional DDR Testing, High Volume Manufacturing (HVM) Test, ATE (Automated Test Equipment), Silicon Debug and Failure Analysis, Test Optimization & Debug, DPM (Defects Per Million) Management, Root Cause Analysis, Product Quality, Test Program Development, Product Introduction, Reliability, Product Engineering, Test Engineering, Customer Requirements, New Product Rollout, Optimization, Root Cause, Communication

Experience

Senior Product Development Engineer

Intel

2022-9 - Present · 4 yrs 1 mo

Penang, Malaysia

Key Responsibilities & Achievements: Own post-silicon HVM test program development and optimization in the MBIST domain, ensuring high-quality silicon validation and alignment with product milestone and PRQ schedules. Analyze silicon failure modes and implement targeted test patches to improve yield and prevent escapes into HVM. Enable Functional DDR test coverage in the HVM environment, addressing customer-specific DPM targets and supporting production ramp. Drive ATE-to-simulation correlation efforts to ensure accurate test behavior and reduce debug cycle time. Collaborate closely with DFT, silicon validation, and manufacturing teams to define and deploy HVM-friendly and high-quality test content. Contribute to continuous improvement of test strategy, automation, and data feedback loops to improve efficiency and product quality.

Product Development Engineer

Intel

2016-6 - 2025-5 · 9 yrs

Penang, Malaysia

Platform Validation Engineer

Intel

2016-5 - 2020-6 · 4 yrs 2 mos

Penang, Malaysia

in 4 short years, i have been trained professionally in engineering field to understand and responsible on a product development cycle from R&D to High volume manufacturing and to customer across different multi national company with wide range of product involvement.