Hartej S

• Spearheading validation of Cadence’s Protium X2/X3 FPGA prototyping platforms, focused on accelerating SoC bring-up and debug cycles. • Develop and validate testbenches by writing RTL to build test cases, followed by full ASIC flow execution including partitioning, synthesis, place & route, and performance benchmarking. • Run real-world SoC and embedded system designs on Protium hardware, handling HW-SW co-design tasks and driving debug efforts in case of failures. • Collaborate with global customers to reproduce issues, analyze root causes, and support resolution — ensuring efficient hardware bring-up and reduced time-to-market. • Work hands-on with FPGA debug tools and verification environments such as Verdi, ChipScope, and custom scripts to automate regression and log analysis. • Contribute to continuous improvement of compile/P&R flows and engage in internal benchmarking to identify performance bottlenecks.

working on the design, assembly,testing, and implementing of electromechanical systems as per project requirements.

Attained my Bachelors of Engineering degree in the field of Mechanical Engineering while also attending the BAHA competition organised by SAE at a country level, coming second and first, consecutively for two years, and also the champion team in National Ronotics Championship held at our college.