HARISH KUMAR D

Technical Lead @ HCLTech

About

 5.6 years of Experience in VLSI Domain  DFX :  Generating Patterns ( ITPP's / stim vectors ) for the Testcases of features like Ultiscan, STF, TAP and IOV at Block level and Validating them.  DFT :  Experience on TestKompress, DFT Compiler, VCS -VERDI EDA Tools  Experience in Handling Block-level Full scan pattern generation and Coverage analysis.  Experience in Simulation using VCS-VERDI Synopsis Tools  Hands on Experience in Scan Insertion, Stitching and compression at block level using DFT Compiler, Tessent TestKompress tools respectively.  Experience in Latest technology Nodes 28nm, 7nm, 6nm.  Coverage Analysis on low test coverage at block level.  Good Knowledge on JTAG, Wrapper cells.  Good knowledge on Digital Electronics and VLSI ASIC flow.

Country

India

City

Karnataka

Industry

Semiconductors

Skill

Shell scripting (Programming Language), Microsoft Office, Microsoft Word, Microsoft PowerPoint, Leadership, Public Speaking, Scan Insertion, scan compression, Automatic Test Pattern Generation (ATPG), Joint Test Action Group (JTAG), VERILOG HDL

Experience

Technical Lead

HCLTech

2025-1 - Present · 1 yr 9 mos

Bengaluru, Karnataka, India

DFT Engineer

Tech Mahindra Cerium Pvt Ltd

2021-2 - 2025-1 · 4 yrs

Bengaluru, Karnataka, India

I have worked in Tech Mahindra Cerium as a DFX Engineer. I have worked on 3 Projects here, My roles are generating Patterns for the Testcases of different features like Ultiscan, STF and TAP and Validating them.

DFT Trainee Engineer

Synapse Design Inc.

2019-3 - 2020-10 · 1 yr 8 mos

Bengaluru, Karnataka, India

I have worked in Synapse Design Techno Innovations as a DFT Engineer. Worked for client, AMD Bengaluru. Worked on two projects, My roles were generating ATPG patterns, Coverage Improvement and GLS.