Hank Huang

• Own technical end‑to‑end validation criteria strategy & Design for Testability, e.g. Arm SystemReady HW/FW compliance, BER for PCIe and xGMI Link, LTSSM Stress, AC/DC/warm-reboot cycling, PCIe switches/retimers, PCIe bifurcation & lane reversal, 3rd-party cables & switches, TSC clocks for 4P systems, RAS testing for CMOS battery life with design for testability, identify test solutions such as boundary scan, LLCR, and TDR impedance mismatch suitable for detecting liquid-cooling design defects impact on CPU's socket qualification in AI rack systems. • Develop and Facilitate Test Technology Summit 2024 including how future Gen-AI agents may impact on system validation, debug, and manufacturing. Examples such as test-driven LLM frameworks that transform requirements + API docs into structured constraints for generating test code for firmware; LLM-based test agents that read requirements / design docs and generate executable tests, with traceability back to MRD/PRD; and AI-powered test case generation using prompt engineering – where LLMs take user stories or requirements and output test cases, steps, and data. • Debug across application → kernel / UEFI → PCIe PHY/Ethernet PHY layers In my role at Lenovo, I focused on validating AI server hardware requirements (PCIe, DIMM, Ehternet) and connecting the dots to AI performance tokens/sec in real-world applications. I developed test strategies/test-plan/test-case Ansible-Python scripts for RoCEv2 over SR-IOV VF to name a few, while also diving deep into Nvidia's GB200+ConnectX-8 requirements qualification NVQual, NVSSVT, NVRASTool, Arm SystemReady, and Nvidia Platform Validation Playbook. My test methodology are integrated system knowledge including AC-coupled boundary scan across power, cooling, and how AI system design might evolve to optimize for Gen-AI influence workload.

• Led a 120-engineer validation & automation organization (Systems Integration, ROMQA, BMCQA, Manufacturing test including Diags and Boundary Scan), delivering cost-effective, high-quality validation for global OEM/CSP customers. • Built Robot Framework + Python OpenBMC automation to validate server management, firmware upgrade flows, and BMC-centric scenarios at scale; introduced continuous refactoring and test-driven development practices. • Hands-on triage of UEFI/BMC, PCIe, Ethernet, and virtualization issues in production x86 data-center servers, including MCA errors, memory failures, SMART, CRC/BER problems, and OS kernel crashes. • Grew and mentored test engineers into SDET-style roles, building a high-performance QA/TestDev team able to own both test strategy and automation tooling. Lead team to debug manufacturing issues using X-ray, AOI, and IEEE 1149.6 Boundary Scan. • Hands-on UEFI/BMC, PCIe, Ethernet issue triage for CSP/OEM business partners in both USA and China. Debug expertise includes Ethernet, PCIe, and hardware performance issues. Issue triage such as hardware processor MCA and micro-architectural errors, memory errors, PCIe errors, SMART attributes, Ethernet errors, TCP/IP errors, MCA recovery, predictive DIMM failure analysis, OS kernel, and lane margin analysis. • Built CSI Taipei including Systems Integration, ROMQA/BMCQA, DevOps SW team by providing technical deep dive and systems engineering training including PCIe/Ethernet Protocol Exercisers, Analyzers, Jammers, industry standards test specs, MindShare, IEEE/IETF, AMI MegaRAC SP-X & OpenBMC, Intel System Debugger & ITP, and OS kernel log analysis. Coach and lead test automation team by providing continuous refactoring, test drive development, and investigate test automation strategy of OpenBMC utilizing Robot Framework and Python.

Prior HPE, I have senior engineering roles across software, networking, machine learning in Microsoft, Intel, Trend Micro, 3Com, Philips Research East Asia, Conversay. After HPE, I deep dived into problem-solving of data center technologies • Designed technical-risk-driven system test methodologies for 25G/100G switches, NICs/RNICs/CNAs/HCAs, aligned with customer use cases. • Performed deep PCIe + Ethernet debug on x86 server and HPC fabrics, including RoCEv2/iWARP performance, auto-negotiation, BMC–NIC MCTP, and DCB (PFC/ETS/DCBX/ECN). • Validated RDMA storage (iSER, NVMe-oF), software-defined storage (Ceph over RDMA), and virtualization (SR-IOV, NPAReP, DPDK/PacketDirect). • Architected and validated line-rate performance for Taiwan’s first three-tier 100GbE data-center backbone lab within HPE Taiwan Design Center. Debug PCIe of x86 server platform & HPC RoCE/iWARP issue and deep dive BMC-NIC issue concerning MCTP over SMBus/I2C/PCIe, Auto-Negotiation 25Gb between IEEE 802.3bj and 25G Ethernet Consortium using JDSU, Intel Server JTAG debugger ITP/XDP, Windows/Linux kernel debuggers. Design technical-risk-driven, customer-focused test for switches/interconnects/NIC/RNIC/CNA/HCA as well as Energy Efficient Ethernet IEEE 802.3az as trade secrets. Design and implement test methodology for NVMe SSD and HPC fabrics (RoCEv2, iWARP, Infiniband), high performance computing MPI HW Offloads, iSER, NVMf HW offload, Software Defined Storage erasure coding HW Offload, Ceph over RDMA Ethernet storage, RSS, LSO, LRO, checksum offload, Data Center Bridging (PFC, ETS, DCBX, ECN), Server Management Protocol MCTP, Network Virtualization VXLAN/NVGRE/Geneve HW offload, Server Virtualization NPAReP & SR-IOV, Intel DPDK and Microsoft Windows Server 2016 Azure VFP PacketDirect Technology Enablement. Physical Layer Compliance using IEEE Layer 1 BERT and Layer 2 Compliant jitter patterns, IEEE 802.3az, IETF RFC2544/2889 protocol testing for Ethernet Switch and NICs using IXIA.

• As SDE, transferred Windows Media video & image compression to silicon partners (Novatek), contributing to the world’s first JPEG XR HW codec. • As BDM, drove OEM design wins (HP, Acer, Asus, D-Link) for Windows Home Server. • As Technical Evangelist, linked engineering, marketing, and ecosystem partners to grow adoption of Microsoft platforms. Senior Software Development Engineer (SDE) for Windows Media - Enabling technology transfer and video and still-image compression algorithm understanding for Windows technology implemented in silicon by semiconductor company Novatek Microelectronics Corp to tape out the world’s first HW silicon for industry standard JPEG XR codec. Business Development Manager (BDM) - Drove brand OEM (HP, Acer, Asus, and D-Link) awareness including business plan & sales strategy for Windows Home Server (WHS). WHS provides the one and the only one platform of home service and DIY cloud storage and home entertainment to enable digital-life style on Windows Client platform. Technical Evangelist - Technical consultant working with both Corporate PR for Corporate Marketing and Industrial Technology Research Institute (ITRI) in Microsoft Technology Center & Microsoft Consulting Services.

• EPM for SMB switches and Wi-Fi routers, working with Accton and Taiwan MOEA/III on converged voice + data solutions. Engineering PM for SMB switch and WiFi residential routers working with Accton Business Development of converged solution for voice and data network Evangelist and Evangelism Marketing consultant working with Taiwan Government MOEA Institute for Information Industry (III) in in 3COM Taiwan Design Center.

• Customized IPv4/IPv6 networking stacks on XScale IXP network processors and prototyped embedded Linux routers with 802.11 IPsec tunnels. Customize various OpenSource IPv4/IPv6 networking stack on Intel reference design using Intel XScale IXP network processor and microcode programming. Debug embedded Linux issue with Xscale 425 using Integrated Circuit Emulator via JTAG controller. Working on BSP and RTOS VxWorks to interface WIFI NIC driver to develop a prototype of Embedded Linux router supporting OpenSource FreeS/WAN 802.11 IPsec tunnels. Utilizing coding discipline from CodeComplete, the Pragmatic Programmer, and Extreme Programming and an advocate for software engineering discipline within community of Intel Taipei Design Center.

• Developed security products (OfficeScan, Linux residential gateway) with focus on profiling, refactoring, and automated testing. I wrote code for virus scanning product OfficeScan and residential secure gateway embedded Linux (Product name: Gatelock) based on Linux iptables and ACLs. Using C, Javascripts, Java and C++ for frontend webUI development and Entity, automatic unit testing, performance profiling and refactoring to increase code efficiency, readability and maintainability.

Kick off developing Mandarin tone recognition software on PDA using cross compiler for ARM platform. I was hired to develop state-of-the-art Mandarin Speech Recognition for PDA smartphone. But due to 911, many *.COM have financial and H1B Visa continuity to hire professionals internationally after a short period of time.

• Member of Philips PHICOS engine team (C-based MFCC, acoustic/language modeling, Viterbi decoding). • Applied mathematical statistics and statistical inference to machine learning for tonal Mandarin LVCSR: o high-accuracy pitch tracking and tone feature extraction, o integrated into LVCSR for Mandarin, resulting in US Patent (US-6829578-B1) and multiple publications. • Awarded Best Paper, IEEE ICASSP 2000 for tonal speech recognition work. Participate in Philips Speech Recognition Engine from Aachen Germany, codename PHICOS. It consists of more than 30K lines of C source code to do MFCC feature extraction and pitch contour, acoustic model training, language model training, and Viterbi decoding. Developed highly accurate real-time pitch tracking and Mandarin Chinese tonal features for Hidden Markov Model of Large Vocabulary Continuous Speech Recognition (LVCSR). Developed papers and US patent (patent number US-6829578-B1) for robust acoustic tone features that significantly help machine learning before major breakthroughs in 2014 by large scale high performance computing and deep learning. My patents and papers are keep referenced by 55 citing patents from the year 2002 it is published until 2017 Won IEEE International Conference on Acoustics, speech and Signal Processing (ICASSP 2000) Best Paper awards announced by IEEE Fellow Alex Acero Paper reviewer for IEEE Signal Processing letters.