Juhan Kim

Semiconductor scaling and compaction for memories, standard cells, high-speed IOs, and voltage regulators. Mar 2022 ~ Present: DMTS (Distinguished Member of Technical Staff) Mar 2011 - Feb 2022: PMTS (Principal Member of Technical Staff) Design Engineer Apr 2010 - Feb. 2011: Circuit design

Circuit design including memory array circuit and memory control/interface circuit.

DDR memory controller and high speed IO circuit design for Tansmeta Corporation's mobile microprocessor including: High-speed interface, and signal integrity analysis for resolving DDR memory controller to memory module reflection noise issues. and Back-bias circuit and low power circuit design for LongRun2 technology (Adaptive Low Power Controller).

High-speed interface circuit design including memory interface and serdes. Memory design including SRAM, DRAM, register file and content addressable memory. Failure analysis for the memory including wafer level and package level.

Memory design including DRAM core, high-speed memory interface and voltage regulator. Involved DRAM design from bit cell, sense am, decoders, voltage regulators, PLL/DLL and interface circuits and ESD protection. Failure analysis for improving memory yield. Reverse engineering including competitor analysis. And Patent analysis.