georgios chatzianastasiou

About

I have graduated with a MEng Degree (300 ECTS programme) from the Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece. At present, I study at Imperial College London as a postgraduate student of the Department of Electrical and Electronic Engineering. The taught course which I follow is "Analogue and Digital Integrated Circuit (IC) Design". My most important areas of interest are: *Digital Circuit Design and FPGAs *Advanced and Parallel Computer Architectures *High Level Synthesis *Compiler Optimizations *Electronic Design Automation *High Performance Embedded Systems You can reach and contact me at: george_cha@hotmail.com georgios.chatzianastasiou16@imperial.ac.uk

Country

united kingdom

City

london

Industry

electrical/electronic manufacturing

Skill

computer architecture, compiler optimization, digital circuit design, eda, fpga, verilog, c, xilinx ise, pspice, mips assembly, matlab, agilent ads

Experience

associate

general hospital of kavala

2014-6 - 2014-8 · 3 mos

Associate in Hardware-Technical Support Office

Education

dyson school of design engineering

design

2016-1 - 2017-1 · 1 yr 1 mo

In-depth knowledge of analogue, mixed signal and digital circuits, in-depth treatment of low power circuits and embedded systems. Gain experience in both the practical issues of device-level design and system-level performance requirements. Design of high performance systems based on GPUs and FPGAs, design of low power and high performance analogue & digital circuits, as well as issues related to communication of systems (optical and RF) and to MEMS and nanotechnology. Activities and Societies: Imperial College Union member

university of thessaly

computer engineering

2010-1 - 2016-1 · 6 yrs 1 mo

Got the basic principles of Engineering, Software Programming & Logic Programming , Problem-Solving, Advanced Mathematics issues. In-depth research in Computer Architecture and Compilers. Thesis: Implementation of Optimizing Transformations in a High Level Synthesis Compiler In this thesis work, we firstly discuss a number of transformations -such as loop unrolling, function inlining and code scheduling- that were implemented in the C-language front end of the CCC high-level synthesis (HLS) tool and present experiments of such transformations using as benchmark the Mpeg2 opensource C language code. These experiments prove that compiler optimizations can have a significant positive impact in HLS tools. Furthermore, the main purpose of this thesis work is to automatically apply loop unrolling technique in order to optimize the C-language CCC tool front end and provide better hardware output. Grade [10/10]. Activities and Societies: Member of Σ.Φ.Η.Μ.Μ.Υ (Union of Electrical and Computer Greek Students Engineers).