Gagana B
Senion DFT Engnieer @ Mirafra Technologies
About
A DFT Engineer with 4.5 years of work experience, who is passionate about the design process flow and has hands-on experience about a part of the manufacturing process which is Design for Testability (DFT) and its components like MBIST, BSCAN, JTAG, Scan Insertion, EDT Compression, OCC insertion, ATPG , LEC Formal Verification in Tessent.
India
Bengaluru
Semiconductors
Automatic Test Pattern Generation (ATPG), BIST, Scan Insertion, Designing digital circuits, DFT, Scripting, Verilog, Very-Large-Scale Integration (VLSI), Digital Electronics, Design For Testability, Perl, Linux
Experience
Senion DFT Engnieer
Mirafra Technologies
Bengaluru
Working on client project on the implementation of DFT techniques.
Senior DFT Engineer
Insemi Technology Services Pvt. Ltd.
Bangalore
Worked on different client project on the implementation of end-to-end DFT insertion and verification techniques like MBIST, BSCAN, IJTAG, EDT, OCC, Scan Insertion, ATPG - StuckAt and Transition pattern generation, DRC Analysis, Coverage Improvement Technique Implementation, LEC - Formal Verification.
Project Intern
Intel
Bangalore
Completed Internship at Intel in DFT.
Education
Vellore Institute of Technology
VLSI
Jawaharlal Nehru National College of Engineering
Electrical, Electronics and Communications Engineering
Gagana B's Contact Information
Phone
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