Gadi Singer

Leading research and development of a new generation of AI guardian technologies.

Lead the Emergent AI Research, driving innovation in machine intelligence and cognition, combining deep learning with deep knowledge structures and symbolic reasoning to materially improve efficiency, explainability, extensibility, and reasoning capabilities of AI systems.

Drove leading-edge inference technologies to HW/SW product implementation. Responsible for the Intel® Nervana™ Neural Network Processor inference line of the Intel® Deep Learning Inference Accelerators and introducing industry-leading, high power-and-performance data center, and cloud products. The inference processor won the Intel Achievement Award (IAA) for its excellence in innovation and execution.

Responsible for architecture and advanced technologies for AIPG product lines and driving corporate alignment and deep learning architecture acceleration across Intel. Established a cross-Intel community of AI technical thinkers and practitioners through series of inclusive internal DL summits. Engaged with the eco-system and media in articulating the strategic evaluation and vision of AI, including the intersection with High-Performance Computing (HPC).

Responsible for the architecture of future IPs and leading technologies for integration in Intel products and foundry including key subsystems such as CPU cores, imaging, security, and audio. In parallel, drove corporate-level processes to recognize the fundamental challenges and opportunities associated with AI in general as well as the vision of Cognitive Computing.

Led the Intel® Israel Development Centers (IDC), of several thousand developers across multiple cities. Drove identification of emerging technology efforts, including creation of the Natural Language Processing (NLP) research team and contributing to the creation of the inference acceleration architecture. Co-led the Intel Collaborative Research institute for Computational Intelligence (ICRI-CI) with the Technion, Hebrew University, Ben-Gurion University and others.

Led the vision, strategy formation, and implementation of a rapid-turn approach to SoC development. Drove a corporate program dubbed ‘6+6’ to materially shorten the duration and lower the effort for creating interchangeable design collateral and the fabric to integrate it. Led the first centralized design-blocks development organization for Soft IP and Hard IP at Intel and drove the interconnect architecture to allow for future nimble integration. As the corporate sponsor for Agile SW development introduced and established advanced industry practices such as Continued Integration at scale.

Led the team responsible for the development and introduction of the Atom™ IP and processors. The Intel® Atom™ processors established a breakthrough technology that delivered a fully compatible IA-32 and x86-64 instruction set, performing at very low power. First Intel® Atom™ (codenamed Silverthorne) provided full x86 compute at under 1W.

Led the technology development organization at Intel Communications Group, under Sean Maloney. As CTO, managed a large engineering organization that delivered communications-related IPs and technologies. Drove technology interactions with key industry players as well as the broader ecosystem on emerging system capabilities and solutions.

Engineering GM, managing the development of ultra-low-power processors, including Intel® XScale ™ technology. This innovative solution was highly competitive with contemporary ARM solutions on top performance and power/performance.

Drove the engineering and technologies for Intel enterprise (servers and data centers) products. Led the introduction and initial ramp of the Xeon® product line including the Pentium® III Xeon® and Xeon® 1.x and 2.0. Completed the Itanium product development and drove the delivery of the first generation. Participated in the customers and market strategic shift in accepting Intel products as enterprise-class leadership solutions at scale. Co-led the activity with Steve Smith (https://www.linkedin.com/in/stephen-smith-79974390/)

Turned-around and redefined Intel’s corporate CAD. Led an organizational transition from a limited design automation support to projects, to a corporate function that collaborates with EDA companies to deliver the best design technology for Intel®. Consolidated multiple development support organizations into the revitalized Design Technology (DT) org. Advocated and drove HW-SW co-design approaches. Was Chairman of the EDA Industry Council, comprised of the CEOs of all large EDA companies at the time.

Relocated to the Bay Area. Led the DA team for the i586/Pentium® project, and later took added responsibility for the program back-end development. Drove innovation in design automation. Won Intel Achievement Award (IAA) for the invention of Schematics Formal Verification (SFV) which solved the challenge of design discrepancies between logic and schematics blocks. Was the first project manager for the P7 project (Intel’s first 64-bit development program).

Drove EDA tools and capabilities for logic design and verification. Was selected by Pat Gelsinger to be part of the 3-person team that created Intel®’s Hardware Description Language (iHDL). The iHDL language and environment were used to design Intel® products’ RTL for two decades. The definition and implementation effort was awarded an Intel Achievement Award (IAA). Also created a novel logic simulation environment called NetGen which was also awarded an IAA.

Joined Intel® to write i387 math co-processor libraries. In support of the upcoming i386 revolutionary microprocessor architecture, drove the SW development work for i386 Assembler & C Compiler. The resulting assembler and compiler were part of the standard SW suite to support i386 deployment at scale.