ed hardy
senior engineer
About
Expert in FPGA development from requirements definition to shipped product. Team lead experience. 4 years experience in ultra low latency data processing. 15 years experience in development roles.
united kingdom
cambridge
semiconductors
fpga, vhdl, programming, python, altera, linux, c++, xilinx, digital design, integrated circuit design, ic, hardware, field programmable gate arrays, testing
Experience
design engineer
ninetiles networks
senior digital design engineer
artimi
VHDL coding of Modem for UWB chip
senior design engineer
axxcelera broadband wireless
Design and implementation of MAC layer for point to multipoint broadband wireless equipment using VHDL/Verilog on Xilinx FPGAs
development engineer
nortel
development engineer
wentworth laboratories
technical lead
solarflare communications
* Technical lead for FPGA RTL group. * Successfully delivered AOE SolarCapture Pro * http://www.solarflare.com/SolarCapture-Packet-Capture-Software
principal engineer
solarflare communications
Technical Lead - FPGA Applications Development Successfully delivered AOE Line Arbitration and AOE Resilient Ethernet applications
senior hardware engineer
activ financial systems, inc.
Team lead - hardware feed handlers and translators. Design and coding in VHDL on Altera FPGAs
senior digital design engineer
staccato communications
Support of RFIC team with new chip - test software development in Python. STA of digital interface using Tetramax
senior engineer
arm
Design Engineer in Media Processing Group
Education
cranfield university
engineering
ed hardy's Contact Information
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