Dwight Ang

Senior MTS @ Maxim Integrated

About

- Device physics expert with over 10 years of experience for high voltage LDMOS, VDMOS , IGBT, BCD, CMOS, ESD , III-V , SOI and SiGe and GaN on GaN JFET device families. - Distinguished Product Engineer with in depth power management circuit expertise. - Accomplished Staff Device Integration Engineer with a track record of deep and strong relationships with Designers and Foundry in achieving Si and III-V milestones. - Versatile technical leader recognized for managing cross functional foundry teams (US, China, Malaysia, Germany) in successful execution and completion of projects ahead of schedule. - Expert at Root Cause Analysis. Proven ability to meticulously and tenaciously identify issues and recommend solutions. - TCAD modeling expert, with fine touch for model tuning to create and validate process flows and predict electrical parameters. - Astute device engineer, skilled in characterization and finalized key parameters of all Power and ESD protection devices . SKILLS . Device Physics: CMOS, BIPOLAR, DMOS, IGBT, III-V, ESD Protection, GaN on GaN JFET . Process Integration: BICMOS, BCD (BIPOLAR CMOS DMOS), BIPOLAR, CMOS . TCAD: Suprem4/Pisces (ATHENA, ATLAS, TSUPREM4, MEDICI), Sentaurus and Decim . Foundry Interface: SVTC, ASMC, INFINEON, PHILIPS, INTERSIL, XFAB, TOWER-JAZZ . Product Engineering: Test Methodologies, JMP software, FIB, Olbirch IR probing, XSEM, TEM, FIB, Analog and Digital Circuits, Solid-State Relays, DC-DC-Converters . Parametric Test: Reedholm, Keithley P4200, HP4145, Focus Test FT1000, Keithley K2636 Labview, HP4284A, Tektronix 576, HPPI , Hanwa TLP . Layout: EXPERT, GDSVIEW, LEDIT, EMASKVIEW, LAYOUTEDITOR

Country

United States

City

Sunnyvale

Industry

Semiconductors

Skill

TCAD, Submicron CMOS Process Integration, BCD Power Process Integration, E-Test Data Analysis and Synthesis, Analog and Digital Circuit Analysis, Olbirch Infra Red Probing, German, Mandarin, Semiconductor Device Physics- CMOS, Bipolar, DMOS, III-V, Electrical Charactrization- Reedholm, Keithley 4200, HP4145, Keithley 900NT, DOE of experiments, Failure Analysis- FIB, RBS, TEM, SIMS, Olbirch, Failure Analysis, Process Integration, Semiconductor Device, Design of Experiments, Data Analysis, CMOS, BiCMOS, Analog

Experience

Senior MTS

Maxim Integrated

2016-8 - Present · 10 yrs 2 mos

San Jose

. Do TCAD and device simulation of high voltage ESD protection devices . Validate electrically consistency of new and used ESD structures through TLP for HBM and MM. . Measure SOA for high voltage ESD protection devices and determine the operating voltage and current ranges. . Make leakage measurements over temperature, room, 85, 125 , and 150C to determine device leakage integrity. . Make Wafer level latchup measurements . Make C-V Tests using B1500A system

Consulting Device Engineer

Avogy | ZOLT

2016-2 - 2016-5 · 4 mos

San Jose , California

Consulting Device Engineer with accomplishments below: . Finalized conditions for Safe Avalanche Test of GaN on GaN JFET for Data Sheet and Final Test. . Finalized parametric curves of GaN JFET including Rdson and Idss over temperature. . Rdson compositional analysis in wafer level over temperature, with root cause of failure. . Extraction of Cosser and Cosstr , providing FAE with better estimates of power dissipation. . Creation of simulation workbook to calculate COSS/CISS for arbitrary doping concentrations. . Utilization of JMP software to generate trend plots, with root cause analysis for rogue points.

Staff Device Integration Engineer-L/VDMOS, BCD, ESD Protection

Semtech

2013-6 - 2015-7 · 2 yrs 2 mos

Camarillo, CA

Successfully led foundry and packaging teams in achieving the following: - Delivery of first silicon for new design wins 2-3 months ahead of schedule. - Yield improvement of 3 major device families to >90% with savings of $1M. - 8in. wafer conversion with savings of $1.5M. - Cost savings on gold to copper wire conversion with savings of $650-850k. - Ran TCAD simulation on new AlGaN ESD protection device with all the process data for fabrication.

Staff Device Integration Engineer - CMOS, BCD, LDMOS, VDMOS, IGBT, BIPOLAR

SVTC

2008-4 - 2012-9 · 4 yrs 6 mos

San Jose, California

Led team of 6 module and failure analysis engineers, by being highly motivational and leading by example. Uniquely skilled at optimization, meticulous with strong intuitional skill based on years of manufacturing and development expertise. Successfully executed the following projects with 3 to 6 fold enhancements: - 0.18um LDMOS BCD project , with project scope of $400k in 2011 to $1.3million in 2012. - 0.18um Low Temp SOI CMOS project with project scope of $500k in 2010 to $3million in 2012 - 0.6um ESD Protection Device project , with project scope of $300k in 2009 to $1million in 2012. - 1.2um 600V IGBT project in 2008, with project scope of $350k. - Created FMEA of SiGe HBT devices.

Senior Device Engineer-CMOS , BIPOLAR, LDMOS

Semtech

2007-10 - 2008-3 · 6 mos

San Jose, California

Resolution of 2 major circuit problems with yield increase >90%. Design rule creation and validation for 30 and 40v device families.

Senior Device Product Engineer - CMOS, BIPOLAR, LDMOS

Quicksil Inc

2003-3 - 2007-8 · 4 yrs 6 mos

Fremont, California

Owned and set up FEOL and BEOL process flows for ESD protection device families, LDMOSFET, and BIPOLAR device families. Improved yield to > 90%.

Senior Device Product Engineer - CMOS, BIPOLAR

Intersil (acquired by Renesas)

2001-3 - 2003-3 · 2 yrs 1 mo

San Jose , California

Characterized CMOS and BIPOLAR device families using Keithley 4200 . Accomplished yield improvement >80%.

Senior Device Product Engineer - LDMOS, VDMOS, CMOS, BIPOLAR

Infineon Technologies

1997-5 - 2001-3 · 3 yrs 11 mos

San Jose, California

- Applied RESURF and Superjunction techniques to develop family of 250-700V LDMOS/VDMOS/IGBT transistors . - Resolved solid state relay circuit and device issues with yield >90%. - TCAD expert (ATHENA/ATLAS). - Foundry interface ( Munich, Villach, Quicksil, Intersil-Harris)