Dulce Cortés Artavia

• Technical lead for the Costa Rica GPU Hardware IP - Tools Flows and Methodology Team. • Front End checks owner and RTL quality expert in charge of ensuring all quality aspects of the RTL design and creating proprietary methodologies and tools.

Full chip Quality Technical Lead and Technical Engineering Manager, leading a team of 12 physical design engineers specialized in the sign-off integration domain including floorplan, static timing analysis and formal verification.

Design quality expert for Intel GPUs. In charge of definition of tools, flows and methodologies for quality assurance across GT, Media, and Display IPs.

Responsible for the hardening of Intel's graphics microprocessor in the 14nm node, driving key aspects of the design flow including synthesis, place and route, and static timing analysis to optimize performance and ensure design integrity.

GRADUATION PROJECT: Modelling of photovoltaic cells and parameters calculation techniques, 2011 • Approved with the maximum score PROJECTS: Design and implementation of a wireless security system, 2010 Design and implementation of the control unit for a tracking robot with objectrecognition, 2010 Poultry incubator digital control unit, 2009 Sun tracking system design and implementation, 2009 Audio multiplexer and mixer system design and implementation, 2009 Error-correcting system with Hamming code, 2008