Divya Kiran Kadiyala

– Architect and evaluate high-fidelity performance models for AI/ML workloads on large-scale distributed systems, driving throughput improvements and latency reductions. – Lead R&D on next-generation HPC/supercomputing architectures, addressing high-impact computational requirements across scientific and industrial domains. – Define technical roadmaps for post-Exascale systems by benchmarking emerging hardware/software stacks and analyzing advanced interconnect and memory technologies. – Design and implement cycle-accurate simulators and emulation platforms to validate SoC subsystems and multi-node architectures, enabling evidence-based design trade-offs. – Drive intellectual property creation by identifying patentable innovations in hardware acceleration and distributed-system methodologies and supporting invention disclosures/filings. – Publish peer-reviewed research in top-tier venues, advancing the state of the art in computer architecture and high-performance computing.

Working on improving memory efficiency and scalability of AI/ML Training leveraging CXL memory

Worked as Summer Research Intern at HP Labs in Networking and Distributed Systems Group.

Worked as Research Intern in Memory Solutions Lab at Samsung Semiconductor Inc. https://samsungmsl.com/

Worked on RISC-V based microprocessor architectures for domain specific AI accelerators.

At Cadence Design Systems, I worked on IR and EM power sign-off tools, collaborating closely with R&D and product engineering teams to develop novel flow methodologies and new feature enhancements for the Voltus® power sign-off tool. My primary focus was on power-grid abstraction and its correlation against SPICE simulations to ensure accuracy and scalability across large SoC designs. I also provided technical support and solution development for Voltus® power sign-off issues for a major hardware company in the Bay Area, helping improve analysis performance and sign-off confidence.

I worked as a Student Research Aide at the VLSI Research Lab, Arizona State University, under the supervision of Dr. Lawrence T. Clark. As part of the TC25 research project, I conducted extensive testing and data analysis on TC25 SRAM memory arrays, collecting data from fabricated test chips and performing statistical analysis to characterize device behavior and variability. This work resulted in two IEEE journal publications. Key Contributions: 1. Investigated SRAM-based Physically Unclonable Functions (PUFs) for device authentication and security. 2. Analyzed random telegraph noise (RTN) effects on SRAM bit-cell stability under varying process and voltage conditions. 3. Designed and executed experimental setups for 6T SRAM blocks on the TC25 test chip, performing detailed data acquisition and analysis. 4. Developed Perl scripts to automate data parsing and statistical analysis workflows for large-scale test data. 5.Designed the physical layout of an LRU register file supporting the Tag Array using the 7nm ASAP predictive FinFET PDK.

Worked as Junior SAP Consultant in SAP User administration and SAP security. - Performed troubleshooting in the technical issues related to SAP ERP Roles and Authorizations. - Performed monthly periodic review and audit works in compliance to organization's Information Security policy. - Performed user administration activities and provided active support to end users. - Prepared the technical and process related documents for Business to review.

Studied Electronics and Communication Engineering.