Dinesh Annayya

building semiconductor solutions in the surveillance cameras for enterprise and consumer applications

SOC Architecture & Integration for wireless Chip

Coordinated 65nm SOC Design,Verification,Synthesis, BIST, SCAN, JTAG and STA activity for a universal TV tuner chip. Activity includes: > Top-level Architecture > Sub block integration - DSP Processor, SDRAM, I2C, SPI, UART > FPGA integration support > DFT methodology/Debug - BIST, JTAG, Full/Compression/OPCG SCAN > Logic Equivalent Checker issue debug > Static Timing fixes > Gate level simulation debug

Project: Atlanta chip sets (A1000/A2000) Description: The Atlanta A1000/A2000 communications processor delivers wire speed IEEE 802.11n WiFi performance and carrier-grade Voice-over-IP (VoIP) with the lowest power consumption and bill-of-materials (BOM) cost of processors in its class. It supports a wide range of applications including voice-enabled gateway routers for home and small office use, as well as IEEE 802.11n WiFi access points. Contribution:  Managed full chip india design/verification team.  Top-level design integration  Full chip timing closure  Full chip DFT-BIST/JTAG/SCAN Methodology.  System level chip bring-up.

Project: EPON Mustang CPE Chip Sets (ME100/ME200/ME200BA/ME300) Description: The integrated, low power FTTH solution targets service providers deploying EPON in CPE, enabling the delivery of triple play services including IPTV. The Mustang chipset supports traffic management, classification and filtering for up to 256 multicast groups, and up to eight different service types. The Mustang chipset integrates packet buffer and program memories in a compact package. Contribution:  Developed full chip verification methodology.  Design of Bride Block  C based verification modules development.  Top-level integration  Full chip timing closure  Full chip DFT-BIST/JTAG/SCAN.  System level chip bring-up.

1) Project: Design and Verification of POSIC2GVC Description: POSIC2GVC is part of Cypress Broadband chip-sets that incorporates SONET frame for OC48/PC12/OC3 with 16 port and UTOPIA, POS-PHY 3 link interface Contribution:  Design of 16 port Generic Frame Tagger block with gate count of 150K. This block has two level protocol comparator to parse and analysis the incoming packet. We have got US patent for the architecture.  Design of 16 port UTOPIA-3/POS-3 receive link layer interface.  Developed full chip verification methodology.  Designed a fast parallel CRC generator and we have received US patent for the same.  Synthesis and Static timing analysis of frame tagger and Utopia/Pos-phy link layer design.  Full chip Scan vector generation using tetramax  Full chip code coverage using HDLScore. 2) Project: Verification of DEMS Description: E1/T1 mapper for OC-1/OC3 SONET/SDH Contribution:  Verification of 8 bit Embedded Processor core. 3) Project: Software for E2/E3/E4 Multiplexer Description: PDH Multiplexer for E2/E4/E4 bit rates. Contribution:  Design and testing of system software written in C 4) Project: Software for E4 Optical Framer Description: PDH Optical framer of E4 bit rate. Contribution:  Design and testing of system software written in C

Project: Hardware and Software of fiber in transmission loop. Description: Fiber in transmission loop is 512 subscriber line concentrator to OC-1 rate on optical fiber. Contribution:  Design of control card  Design and testing of system software written in C