Dinesh Reddy Ankireddy

Verified key components of the GPU memory subsystem, including a graphics memory interface unit responsible for converting cache and IO transactions into XEFI protocol operations, and a companion unit for capturing critical transaction data for post-silicon debug and replay. • Owned functional coverage closure across both units, including development of coverage modules, gap analysis, and targeted stimulus/environment updates to meet closure goals. • Authored and maintained detailed verification testplans, collaborating with micro-architects and RTL teams to ensure full spec alignment. • Built and enhanced UVM-based environments, contributing constrained-random sequences, monitors, scoreboards, and reusable coverage components. • Adapted the verification environment for new projects, modifying testbench infrastructure to support architectural differences and enable successful bring-up. Regularly ran regressions and conducted root cause analysis using Verdi, debugging both RTL and testbench issues. Developed and debugged SystemVerilog Assertions (SVAs) to verify protocol compliance, control signal behavior, and timing relationships. • Verified complex scenarios including atomic transactions, partial writes, backpressure, ID reuse, and other stress conditions across multiple outstanding requests. • Refined memory-intensive SystemVerilog assertions to reduce resource consumption while maintaining verification accuracy. Strong collaboration with RTL, architecture, integration and post-silicon validation teams to drive verification sign-off.

Advisor: Prof Dr. Swarup Bhunia Working as a Researcher in Hardware Security domain and formal verification. • Engineered a tool using Python for structural and formal verification of gate-level netlist designs, improving accuracy and reliability by 90% compared to Cadence Conformal LEC for ASIC designs. • Resynthesized designs with modified instances and net, port names, added DFT logic, and PPA analysis using Genus, performed LEC with Cadence Conformal to find cut points of designs, and identified an 80% failure rate across various benchmarks. • Automated ASIC LEC verification using shell scripting and TCL in a Linux environment, achieving 100% automation for LEC. • Mapped an IP to FPGA ZCU102 UltraScale+ SoC using Xilinx Vivado and Vitis, ensuring seamless integration and optimal performance. Achieved 100% reliability by validating and debugging the system, enhancing stability in real-time applications.

Designed and fabricated integrated circuit layouts on PCB for missile launcher components. Gained proficiency in utilizing EAGLE software for the design of fundamental circuits.

Fall 23 courses: Hardware Security and Trust Reconfigurable computing (FPGA) VLSI circuits and technology-1 Spring 24 courses: Advanced VLSI circuits and technology CAD for Hardware Security Validation Future of Microelectronics Fall 24 courses: Hands-on Hardware Security Formal Methods Research thesis Spring 25 Courses: Research thesis

Earned First Class Distinction