Dev D.
GPU Implementation @ Apple
About
* 20+ years as Engineering Manager & Tech Lead in building productive teams and successful chips * Expertise in SoC & digital IP backend design including STA, timing closure, physical design, synthesis and verification * Worked extensively with ASIC customers based in Germany, Finland and US * Experienced in working with cross-functional teams to achieve objectives
United States
Austin
Semiconductors
Python (Programming Language), Project Management, Engineering Management, Customer Relationship Management (CRM), Technical Leadership, Customer Engagement, SoC, ASIC, Static Timing Analysis, Physical Design, Low-power Design, Power Management, UPF, Power Estimation, Equivalence Checking, TCL, Perl, Automation, Team Management, Communication
Experience
GPU Implementation
Apple
Austin, Texas, United States
Physical Design Engineering Manager
Intel
Austin, Texas
Engineering Manager in customer interface role
Intel
Tampere Area, Finland
Worked from Finland to support SoC designs as customer interface manager / liaison
Engineering Manager
Intel
Pune
* Technical manager for netlist-to-tape out execution of networking ASICs for external customers
ASIC Design Manager
LSI, an Avago Technologies Company
Pune Area, India
* Technical lead for netlist-to-tape out execution of internal (Storage) chips and ASICs for external customers * Primary person for technical communication with customers: based in Germany, US * Drove technical decisions, problem solving, face-to-face meetings
ASIC Design Engineer Staff
LSI, an Avago Technologies Company
Pune Area, India
* Led Timing closure & STA for full chips * Developed and drove flow automation and setup for predictable execution * Led activities on low physical design, power implementation, equivalence check, ECOs, etc.
Senior Design Engineer
Texas Instruments
Bengaluru Area, India
* ARM based IP integration, verification and physical design: leading a team of ~4 contract engineers * Synthesis, physical design & timing closure of TI DSP and ARM processors * Clock tree construction and timing closure of full chip * Contribution to automation flows
Education
Savitribai Phule Pune University
Electronics and Telecommunications
Dev D.'s Contact Information
Phone
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