Deepti Bhaskar

Work as a Physical Design/Structural Design Engineer in the Memory Subsystem team at Intel. 4+ years of experience in executing high speed complex blocks. Worked extensively on Design Planning, Auto Place Route, CTS/ CTMESH, STA analysis, Multi voltage design, layout using SNPS tools. Currently leading the SD execution of a few small blocks. Duties include mentoring, driving the design plan, timing, layout and other flows. Also work on Full Chip (FC) roles involving Leading and Managing the team to sign off on various domains. FC domain experience - Noise , Slope & Cap Violation, Layout checks (DRC), Logical/Functional Equivalence Verification. 1+ years of experience in Mentoring and Ramping up New hires and Interns.

An introduction to electrical and electronic devices, circuits and systems including software and hardware focusing on a real-world project. Worked on teaching freshmen students how to solder and mentored them on basic C++ coding for their final projects.

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A 10 week summer Internship where I worked on developing AMBA AHB (Version 3.0) protocol in System Verilog using ModelSim.

Was introduced to various Soldering techniques and dealt with failure analysis of chips.