Dedeepya Pedapenki

Product Development Engineer - Product Owner @ Altera

About

Product Development Engineer-Product Owner with 10+ years of experience progressing from post-silicon validation and characterization to end-to-end ownership of silicon test content and HVM readiness. My career spans taking products from post-silicon bring-up through high-volume manufacturing (HVM), with increasing responsibility for test architecture, validation strategy, and yield/quality outcomes across SORT and CLASS flows.My specialization is Array Content, Repair, and Fuse Validation, where I evolved from developing and validating test modules to owning repair flows, reject validation, and screen strategy that measurably improve outgoing quality (DPM) while reducing test time. I have supported both client and server product lines and consistently operate in roles requiring end-to-end technical ownership, closing the loop between silicon behavior, test implementation, and production data.Core strengths:• Post-silicon debug and validation (array and functional failures) in HVM environments• Test program ownership: infrastructure, voltage/timing/channel assignments, and across-temperature coverage• Repair module integration (hard defect and VMIN/read-assist conditions) with fuse string validation on ATE• Yield and quality ownership: bin analysis, PHI improvement, reject disposition (IM/QA/PPV), and cold-socket elimination• Product lifecycle ownership from tape-in through PRQ and production maintenanceTechnical focus areas:Post-silicon debug, ATE validation, MBIST/SRAM/RF arrays, array raster and shmoo, VMIN repair, redundancy, fuse programming and validation, screen strategy, DPM, yield debug, reject validation, pilot lots, SORT/CLASS, HVM ramp, and full product lifecycle (tape-in → PRQ).

Country

United States

City

Austin

Industry

Semiconductors

Skill

Analytical Skills, Test Program Development, Testing, Test Automation, Field-Programmable Gate Arrays (FPGA), Product Development

Experience

Product Development Engineer - Product Owner

Altera

2022-5 - Present · 4 yrs 5 mos

Austin, TX

• Test Program Owner for FPGA-Class HVM Products (Full Product Lifecycle) o End-to-end ownership from tape-in through PRQ and production ramp o Defined and developed universal test programs for HVM manufacturing o Owned test program infrastructure and module development aligned to minimum test requirements for SORT and CLASS o Led fuse and binning validation and OPN handling to meet customer requirements • HVM Quality, Yield, and Test-Time Optimization o Drove test program quality analysis with focus on outgoing DPM and test-time reduction o Developed intra-DUT test programs for scalable HVM execution o Owned yield analysis and reject validation, driving PHI improvement and production learning

Sr. Product Development Engineer

Intel

2019-5 - 2022-4 · 3 yrs

Austin, TX

• Post-Silicon Array Content Owner – Client and Server Products o Owned development and validation of array sub-flow modules at SORT and CLASS o Executed raster data collection on standing die at CLASS for debug and characterization o Led reject validation at IM, QA, and PPV for array content failures o Implemented screen strategies at SORT and CLASS to improve outgoing DPM and enable cold socket elimination o Performed data analysis and delivered test-time improvement updates for array content • Pre-Silicon Content Development – Server Products o Performed vault linking and library imports across sister products with line-item creation o Executed emulation and simulation of array content traces to support content readiness • Post-Silicon Repair Module Owner – Client and Server Products o Owned hard defect implementation on configurable BIST arrays at CLASS o Delivered VMIN repair implementation at SORT and CLASS for multiple read-assist conditions as part of yield improvement efforts o Executed array repair fuse string validation at SORT and CLASS

Product Development Engineer

Intel

2015-7 - 2019-4 · 3 yrs 10 mos

Hillsboro, OR

• Executed characterization and validation of MBIST memory arrays on test chips using modular testers at CLASS • Generated content for KS, redundancy, and raster test conditions for SRAM and RF arrays • Performed standing die shmoo validation and volume data collection and analysis for multiple read and write assist conditions • Supported test program integration and validation for test chips on CMT and HDMT • Performed test program conversion from CMT to HDMT on client products • Executed array content pattern conversion and module flow updates using pattern modify files, followed by platform validation • Supported pilot lots through test program integration/validation and data analysis for bin switches