david pena

* During my early years with Cadence, I managed the delivery of custom, semi-custom, and ASIC-integrated circuit architecture, defining and negotiating work scope and executing design and methodology services to align with customer requirements. I successfully structured and carried out solutions sales, achieving margins of 50% and higher while meeting annual multimillion-dollar sales quotas. * PRODUCTS: * ✓ Complex Programmable Logic Devices * ✓ 900 MHz IC * ✓ Networking & Telecom * ✓ FPGA ports * ✓ Gigabit channel model licensing

My roles as the Cadence Memory Model JEDEC representative, the Cadence Memory Vendor Program Director and my participation in groups like the Flash Memory Summit Conference Advisory Board enable me to define high impact product strategies. A primary criterion for business growth is combining market analysis of system architecture trends with memory vendor roadmaps to ensure the Cadence Memory Model provides substantial value. My primary focus is on verification and validation of emerging memory hierarchies (e.g. LPDDR, DDR, HBM, GDDR, NVDIMM, NAND, Embedded/Flash, SD, EMCC). KEY CONTRIBUTIONS: ✓ Influence leading memory manufacturers to accelerate the adoption of emerging memory technologies. ✓ Drive product strategy to improve MSS leadership with quality, advanced verification, and market-aligned product definitions. ✓ Collaborate with and advise Executive Management and R&D to lead introduction of differentiated technology.