David Kliebhan

David Kliebhan

Sr. FPGA Design Engineer @ Mantaro Networks, Inc.

About

Expertise in FPGA, ASIC, software, PCB, and product design. • DSP, complex data paths, state machines, modelling • SoC implementations, embedded software • Video, RF, datacom, serial interfaces • Verification, hardware debug, manufacture test • VHDL, Verilog, C, C++, C#, MATLAB, Python

Country

United States

City

Greater Philadelphia

Industry

Defense & Space

Skill

ASIC, Digital Signal Processing, VHDL, Application-Specific Integrated Circuits (ASIC), Python (Programming Language), Embedded C++, Embedded Software, C (Programming Language), RTL Design, FPGA Development, PCB Design, C#, Matlab, Product Management, New Product Design, Entrepreneurship, Verilog, C++, FPGA, Electronics

Experience

Mantaro Networks, Inc.

Sr. FPGA Design Engineer

Mantaro Networks, Inc.

LinkedIn
2024-6 - Present · 2 yrs 4 mos

Primary FPGA contributor to space-time coding instrument. • Custom VHDL programmable calculator for complex-valued matrix operations • Calculator syntax, compiler, and coding • Frequency, phase, and amplitude estimations • Nelder-Mead and Golden Section search algorithms • Python modelling, verification • VHDL Quartus, Modelsim

GEOST, a LightRidge Solutions Company

FPGA Design Engineer

GEOST, a LightRidge Solutions Company

2023-9 - 2024-5 · 9 mos

Developed DSP firmware for SDA satellite payload. • IIR filter, threshold calculation, pulse detection and measurement • Python modelling, verification • VHDL, Vivado, Python, Xilinx Zynq-7000

AccuTennis

Founder, CTO, Lead Developer

AccuTennis

2016-11 - 2023-4 · 6 yrs 6 mos

Greater Philadelphia Area

Lost a match on a bad call and AccuTennis was born. Originated an innovative line call and player development system for tennis courts. Primary contributor to system architecture, hardware, and software implementation. Product description and videos at accutennis.com. • Created the overall concept, technologies, and business model • Developed custom camera PCBs, VHDL, and C++ on Cyclone V SoC • Coded C++/OpenCV on Raspberry Pi • Coded C# system-level processing and simulation environment – real-time object filtering, correlation, identification, physics, tracking; calibration; match and drill automation; stats, analysis, video clip generation; scoreboard data, plots, video playback, mirroring; voice prompts; player gesturing; UI processing; db design and interfaces; system setup, configuration, diagnostics, management, error handling, and reporting • Coded Python scoreboard server and graphics • Supervised UI app and back-end website • Designed front-end website • Created interactive drills with voice and scoreboard prompts • Pitched and sold company to investors • U.S. Patent 9,737,784

Sealevel Systems

FPGA Design Engineer

Sealevel Systems

LinkedIn
2020-10 - 2021-2 · 5 mos

• Lead FPGA engineer for PCIe card • Verilog, VHDL, Lattice ECP3, HDLC integration, PCB definitions, board bring-up

TESCO Metering

Embedded Software Engineer

TESCO Metering

LinkedIn
2018-2 - 2018-8 · 7 mos

C++ and VHDL for power measuring instrument.

Datalogic

Sr. FPGA Design Engineer

Datalogic

LinkedIn
2009 - 2016-10 · 7 yrs

Telford, PA

Lead FPGA developer for high-speed industrial bar code scanners and laser dimensioning instrument. Contributed to R&D projects.

Mantaro Networks, Inc.

Principal Hardware Engineer

Mantaro Networks, Inc.

LinkedIn
2005 - 2009 · 4 yrs

Germantown, MD

• Worked with new and existing customers on turn-key products • Developed FPGA for RF transceiver board

Sandgate Technologies, Inc.

Sr. ASIC Design Engineer

Sandgate Technologies, Inc.

1998 - 2004 · 6 yrs

Downingtown, PA

Developed data link layer and IPsec functionality for full-stack TCP/IP hardware acceleration ASIC.

Netvantage, Inc.

Sr. ASIC Design Engineer

Netvantage, Inc.

1997 - 1998 · 1 yr

Allentown, Pennsylvania

• Lead engineer for multi-port Ethernet MAC ASIC • Contributed to Ethernet switch ASIC

Quanta Research, Inc.

Sr. Design Engineer

Quanta Research, Inc.

1990 - 1997 · 7 yrs

Fort Washington, PA

• Developed HDL for ATM switch and network adaptor ASICs • Lead hardware engineer for desktop switch product line

Education

Bucknell University

Bucknell University

LinkedIn

Electrical Engineering

David Kliebhan's Contact Information

Email

******@***.com

Phone

(**) *** ****

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