Darshan Satyamurthy

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Client: Intel Corporation Key Responsibilities: Developing and implementing DFT architecture for the client Working on clocking architecture for the entire project Working with designers and DV team to integrate DFT implementations, verify and review verification coverage. Also run various checks Handling schedules and supporting multi-functional engineering effort Working with rest of the team to document DFT specifications Generating structural test patterns and analyzing and improving scan coverage Work with various stakeholders to ensure the DFT architecture is correct.

Creating a PCIe subsystem, Work closely with IP teams to integrate the PCIe gen3 and gen4 IP's into subsystems such as PCIESS and Type-C subsystem Work closely with Pre-Si Validation on initial PCIe bring up and fix any RTL bugs. Design any glue logic if required. Analyze any Design to RTL mismatches through multiple Quality checkers. Work closely with Physical Design to fix any timing violations.

• Working on RTL Design for Display Design team on next generation SoC for Tablets and Phones. • In my role as a Design Engineer, I design the architecture for some of the display features based on the spec and customer requirements. • Work with the Validation teams to make sure the features are being tested correctly and in line with the design and spec requirements. • Responsible for Synthesis using Design Compiler and Formal Equivalence checks using Cadence LEC. • Worked with the other designers in the team to make sure we have added correct constraints during Synthesis like Multicycle paths, False paths. • Responsibilities also included running Formal Equivalnce and making sure the RTL and netlist are matching. • Participate in Silicon Bring up when the silicon first arrives in lab. • Worked closely with Architecture team to make sure that our design meets the specifications.

• Worked on System Validation for 4th Generation Intel Core CPU. • In my role as a Validation Engineer, I identified and debugged multiple sightings often resulting in CPU Bugs. • Worked on Processor Bring up, validating and debugging from Prototype to Production. • Developed new tests for new technologies to ensure proper silicon operation as defined by the architecture or chip specifications. • Was responsible in designing some of the tests for SV and making sure those tests were run on the right configurations. • Worked closely with Architecture and Design teams to debug silicon failures in the lab.

• Worked with System Characterization on High End and Mid Range Multicore-Multiprocessor Systems. •Was also assigned to automate System setup, Initial program load, Link[I/O] setup, Lab environment setup, Measure data, using Perl scripting.