darren slawecki
principal hardware engineer- team lead, product enabling and ramp team
About
Principal Hardware Engineer | Architect and Implement DFT and DFD | ►Silicon Debug | Semiconductors
united states
santa clara
semiconductors
debugging, dft, dfd, silicon validation, soc, microarchitecture, microprocessors, circuit design, pll, test strategy, test equipment, perl, test engineering, unix, bist, testers, scan, semiconductors, hardware, testing, system on a chip, application specific integrated circuits, integrated circuits
Experience
principal hardware engineer - dfx architect, many integrated cores design team
intel corporation
principal hardware engineer- team lead, product enabling and ramp team
intel corporation
* ►Pathfinding Lead: 10nm Server Products (Xeon, Xeon Phi, Micro-Servers) * Analysis and improvement of DFT and DFD architectures for efficient post-Silicon debug * Spec out pre-Silicon Validation test cases to avoid escapes to post-Silicon * Enabling of Tester Debug Readiness & planning - hardware, software, new methodology development * ►Post-Si Debug Lead: 2nd Generation Xeon Phi (code name: Knights Landing) * Drove Post-Si debug execution, characterization, Si debug (pattern+circuit), Vmin/Fmax improvements * Planning for post-si readiness including hardware, software, methodology, partner collaboration
Education
lehigh university
electronics engineering
drexel university
electrical engineering
darren slawecki's Contact Information
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