Chin How Kung

Test Engineer

About

1. Expert in high speed IO Test Contents like PCIE, DMI, FDI, USB3, SATA, MOCA, DOCSIS Physical layer. Well understand the usage of DFT which design for High speed IO. Did pre-silicon works like RTL validation, simulation, VTPsim RTL validation, pattern conversion, and test code development. Done post-silicon which involve Si debug on Tester, test content implementation, characterization, yield improvement, test time reduction, etc 2. Did scripting through perl, python for automation to improve efficient of the jobs. 3. Well experiences on Test program (TP) development, qualification and released to Manufacturing. Well understand on TP components line TP flow, timing, level, pin, socket, etc 4. Experiences in HVM improvement especially on Test Time Reduction and QA for cost reduction. 5. Hardware experience: a. Tester CMT T2000 (Advantest Tester) b. Tester HDMT (Intel Tester) c. Summit Handler, V8 Handler d. TIU 6. Other: a. Programing language: Python, Perl, C++, Excel Macro VBA. b. Analysis software: Microsoft, Jmp c. OS: Window, Unix

Country

Malaysia

City

Penang

Industry

Semiconductors

Skill

Experience

Test Engineer

Broadcom Limited

2016-10 - Present · 10 yrs

Penang, Malaysia

Key Role and Responsibilities: - Develop and validate test program on ATE tester in order to test parts in either wafer level or package level. - Optimize production test program for yield improvement and test time reduction. - Collaborated with Product Engineers, Failure Analysis Engineers, and Quality Assurance Engineers for product qualification and customer returned parts. - Validate New Device Interface Board (DIB) for engineering and production usage - Release program to Contract Manufacturers (CM) for production run - Support CM for production run and any manufacturing issue. Key Achievements: - Developed, validated and implemented new modules/tests into production test program to screen faulty parts. Released high quality test programs to production. - Well plan to distribute ~30 new DIB to 6 CM to support production. - Test time reduction on multiple products to save cost and resources. - Root caused and resolved issues raised by customers by working with designer and counterpart. - Developed characteristics test program to collect data, which was a prerequisite for production worthy test program to be released. Platform: Tester - Teradyne UltraFlex Prober - TEL and Semics

Product Development Engineer

Intel

2010-10 - 2016-10 · 6 yrs 1 mo

Penang, Malaysia

a. 2010 to 2012 – startup an SOC product as TPI lead, level owner and PCIE IO test content owner. Continue Own PCIE for another SOC product. Delivered quality content to beat 99.9% yield. b. 2013 to Q2’2014 – Start work on a new complex SOC products. Owned 3 big content as PCIE gen2 and DP (2 IP) content owner. Involved in pre-silicon validation, xIU design, RTL/VTPsim validation. Successful enabled full content with efficiency automation method during 1st Si debug. c. Q3’2014 to Oct 2016 – change field to work as pattern conversion tool developer. Which developed Infrastructure to support content owner and Intel Customer on pattern conversion and validation.

Product Engineer

Intel

2005-4 - 2010-10 · 5 yrs 7 mos

Penang, Malaysia

a. 2005 - as an owner to sustain on a CPU product. Handler all Test Program release and lot disposition to support output Max b. 2006 - Major functions are on driving HVM improvement (TTR, OLB and EQA) c. 2007 - Successful start a CPU product. Chair TTRWG, successful drive to achieve shortest test time (4.5s) for the product d. 2008 - Worked as content owner for PCIE/DMI/FDI. Using high speed LB (DFT) for FDI. Develop test for PCIE/DMI gen2 (5G) to strobe on tester which using 6.5G card. e. 2009 - Start up another CPU product. Worked as TTR owner and EQA owner. TTR TP released after PRQ + 2 months with 44% test time saving. EQA 1:10 skip lot achieved after PRQ + 3 months.