Chien-Hui Christina Liao

Work with Architects, RTL/IP Designers and Physical Design Teams to perform power analysis/reduction/rollup. Develop SOC process, power and performance modeling python‑based infrastructure to build workload‑based SOC power modeling and power-constraint performance projections. Work with thermal/silicon/validation team to study pre‑and‑post silicon correlations. Pathfinding for Cobalt SoC family for general purpose server in Azure.

Xeon Performance Group • Work with performance architects, circuit designers, process developers, thermal/reliability engineers and product marketing to optimize the system‑level performance and offer highest value of product mix (roadmap and custom).

• Focus on statistical techniques for developing power, performance, and bin‑split projection tool with process variations, through working with CPU, GPU, system designers and architects, and process engineers across organizations. • Responsible for methodology development, software quality, day‑to‑day maintenance of the tool (100,000+ lines of C++ code), and delay/leakage circuit simulations with process variations. • Automate pre‑ to post‑silicon data/model correlation, achieving better accuracy and TAT (weeks to hours).

Focused on pre‑silicon to post‑silicon bin‑split model correlations/transitions of Intel products

Design for Testing Group, Design Sign-Off Div., Design Technology. Developed statistical techniques (data mining and machine learning) to predict testing failures with stress‑test data.

Dept. of Electrical and Computer Engineering. Developed an online thermal‑constrained task scheduler for 3D multi‑core processors with thermal‑pattern‑aware voltage assignment and vertical‑grouping voltage scaling.

Design Automation Dept. Developing algorithms for placement-and-routing problems of IC design.

• Dissertation: Study on Thermally Constrained Task Scheduling in Homogeneous 3D Multi‑Core Processors. • Focused on algorithm and machine learning for OS‑level thermally constrained task‑scheduling to optimize throughput‑and‑energy of 3D MCPs. Developed 3D IC scan‑chain ordering algorithm to reduce wire/power cost. • Cloud Computing: Fall detection by an SVM‑based cloud system; Used data mining for a social searching engine. • Focused on unsupervised learning and mathematics ILP‑based methods to analyze test data and IC diagnosis.