Chi Zhang
Research Scientist @ ByteDance
About
Initiator of verl project. https://github.com/volcengine/verl https://sites.google.com/view/chizhang-usc/
China
Shanghai
Computer Software
Computer Architecture, FPGA, LaTeX, Python, C++, Java, Matlab, C, Linux, Verilog, SystemVerilog
Experience
Research Scientist
ByteDance
Shanghai, China
RLHF infra
PhD Student
University of Southern California
Greater Los Angeles Area
Research PhD Intern
eBay
San Francisco Bay Area
Optimizing search engine indexing
Education
University of Southern California
Computer Science
Research interesting: Deep learning architectures. Deep learning applications.
University of Southern California
Electrical Engineering (Computer Engineering)
KTH Royal Institute of Technology
School of Information Communication and Technology
Completed Courses: IK1550: Internetworking Bachelor Degree Thesis: Modeling and Verification of All-digital Phase-locked Loop
Southeast University
School of Information Science and Engineering
University of California, Berkeley
Electrical Engineering and Computer Science
Completed Courses: CS 70: Discrete Mathematics and Probability Theory EE 141: Introduction to Digital Integrated Circuits EE 229A: Information Theory and Coding
Chi Zhang's Contact Information
Phone
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