Cheng-Chieh Hsieh

Department Manager, Pathfinding for System Integration @ TSMC

About

- 20+ years of industrial experience in advanced packaging technology development * Extensive hands-on experience in wafer-level process integration, technology qualification and design rule formulation in CoWoS®, InFO & SoIC® and their derivative technologies. * Outstanding thermal & thermomechanical numerical analysis and characterization capability in a variety of advanced IC packaging technologies. Architect of two advanced packaging thermal labs and one advanced packaging mechanical and reliability lab. - Proven track record of success in strategic thinking and execution * Initiated, enabled, and promoted the business of embedded power passives (DTC & IVR) to enrich value features and fortify technology resilience of CoWoS® & InFO. * Formulated and executed the development roadmap of high-power cooling technologies in the best interests of the company. - Recognized leadership in cross-team collaboration * Demonstrated capability of defining team’s directions, implementing problem-solving strategies, and coordinating cross-team workforce to achieve goals on time. * Notable performance in leading cross-organizational collaboration to meet customers’ expectations and achieve business triumphs.

Country

Taiwan

City

Hsinchu City

Industry

Semiconductors

Skill

Thermal Management, Reliability, ASIC, Matlab, Thermal Analysis, Electronics, Finite Element Analysis, Labview, ANSYS, FMEA, Heat Transfer, Process Engineering, Process Simulation, Manufacturing, Engineering, CFD, Cross-functional Team Leadership, Six Sigma, Design for Manufacturing, Testing

Experience

Department Manager, Pathfinding for System Integration

TSMC

2021-3 - Present · 5 yrs 7 mos

Pioneer a wide spectrum of thermal management technologies from chip-level to system-level to meet the high power and power-density computing requirements in 3DIC & HPC/AI applications and accelerate their deployment.

Program Manager, Process Integration

TSMC

2019-1 - 2021-3 · 2 yrs 3 mos

Developed various wafer-form packaging technologies derived from InFO & SoIC™ to meet customers’ product requirements in PoP, 3DIC, and heterogeneous chiplet integration. Also actively participated in strategy planning to expedite the adoption of new technologies by customers.

Program Manager, Power IC Business Development

TSMC

2016-9 - 2019-1 · 2 yrs 5 mos

Coordinated cross-organizational collaboration in RD resource prioritization, fab capacity allocation, and EDA/IP support alignment to enable business in advanced power management IC and integrated passive device based on ex ante cost breakdown, demand forecast and market analysis.

Manager, 3DIC Analysis

TSMC

2009-5 - 2016-9 · 7 yrs 5 mos

Responsible for 3DIC-related thermal and thermomechanical modeling methodology and characterization metrology development to enable model for process/yield, model for reliability and model for design. Work closely with module and integration teams for process and design improvement to expedite the 3DIC technology development. Extensive customer engagement to provide timely and quality technical support.

Senior Packaging Engineer

Intel

2005-6 - 2009-5 · 4 yrs

Phoenix, Arizona Area

Focused on packaging thermal solution improvement and performance characterization. Delivered risk assessment and guidelines for solution improvement and published technology and product thermal specification for product enablement. Recipient of Intel Achievement Award 2008 for USD$91M saving on PTIM enablement for low-cost CPU.