Cesar Philippidis

•Designed a PXIe based high speed carrier board to support Agilent’s next generation modular ultra low phase noise synthesizer with fast tune settling times. The carrier board consists of Xilinx V6 FPGA, PCIe - Gen 2 bus (4 lanes), DDR3 Memory, PXIe controls, and power conditioners. This carrier board can also support sampling clock of >1GHz for high speed ADC applications. Implemented a novel custom high speed interface to allow external control of the hardware without using conventional PCIe or PXIe control schemes. This product is currently in pilot run. •Performed architecture definition and project technical leader responsibility of various ruggedized (conduction cooled) low power wideband high speed search emitter detector systems with DF capability utilizing FFT, DDC, and customized search algorithms in an 8 slot 3U Compact PCI form factor chassis. This task involves performing hardware and software tradeoff analyses for optimum system performance, risk mitigation, cost, and manpower requirements. Also responsible for designing and implementing the digital hardware (circuit cards and backplane) using Xilinx V5 FPGA, Spartan 3AN FPGAa, and CPLDs with sampling rate greater than 128 MHz. Technical leadership includes overseeing design and development efforts of the hardware, FPGA, RF, mechanical, and software. Also included coordinating turnkey fabrication and assembly of all circuit cards using mixed lead and lead-free components that includes the chassis fabrication. This program was executed in less than twelve months from initial system design to field trials of five systems, on budget and ahead of schedule. •Performed architecture definition and project technical leadership for a battery operated wideband search emitter detector systems using FPGA and OMAP processors. Supervised development of the hardware unit (Digital, FPGA, RF, and mechanical and software efforts).

• Lead hardware engineer for a risk reduction high dynamic HF receiver program. The risk reduction program included demonstrating a beamforming technique for 128 sensor element. Performed system analysis of transmitting digitized HF data from an array of antennas to a beamformer processor over a distance of > 2 km using fiber optics technique. Designed various digital functions (Array Simulator, Beamformer, FFT, high speed interface, and etc.) on COTS boards using Virtex II 6000 series Xilinx FPGA. The FPGA designed was coded in VHDL. This task commenced two and half months behind schedule of a seven month development effort and was completed on time for the demo.

• Lead Task hardware engineer for an airborne Electronic Support Measurement system. Defined and implemented a system architecture that incorporates several capabilities into a single chassis while enhancing system performance and reducing overall unit size, weight, power, and cost. The task involves working closely with all engineering disciplines, reviewing system requirements, performing tradeoff analysis, functional partitioning and defining board functions. • Performed architecture definition, hardware design and implementation, of a second generation narrow band high speed digitizer board for an ELINT/ESM system based on multiple TMS320C6415 processors, digital filter, and Altera 20K600C FPGA using FBGA technologies on both sides of the board with clock speeds in excess of 100 MHz. Project was completed on schedule of 14 month and within budget. PWB was 18 layers and 100% functional on first turn.

• Performed architecture definition and hardware design of a high speed Programmable Multi-Rate Digital Channelizer board utilizing Polyphase filter, FFT, PAN Processing, and customized search algorithms. The hardware employs several Altera 10K-100 FPGAs, ISP- EPLDs, Motorola DSP56309 chip set, ASIC, and CMOS using SBGA and SMT components on both sides of the board for system flexibility, size constraint, and power conservation for conduction or convection cooled chassis. Additional responsibility included qualifying, supervising, and coordinating various 18 layer PCB layout, fabrication, and assembly vendor activities. Within this responsibility, reduced PCB layout schedules from 5 months to 4 weeks, PWB fabrication cycle reduced from 14 weeks to 3 weeks, and increased circuit card assembly yield to 96% with 5 day turn.

• Performed architecture definition of various wideband high speed search detector systems utilizing odd-point FFT and customized search algorithms. This task involved performing hardware and software tradeoff analyses for optimum system performance, cost, and manpower requirements. Also responsible for designing and implementing hardware using EDA tools, writing C code for testing, and supervising software development task. The hardware employs Altera FPGAs, Butterfly DSP chip set, and CMOS using SBGA and SMT components for system flexibility, size constraint, and power conservation. • Designed SOI Qualification and Background Map hardware for a wideband high speed search processor. This circuit card, based on user selected parameters, qualifies SOIs on cell by cell basis for the entire wideband spectrum. The design utilized high speed Altera FPGAs and CMOS components for system flexibility and power conservation.