calvin yang

calvin yang

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About

楊正光 Calvin C.K.Yang * Over 10 years in semiconductor company --product / testing / Quality / Package /process * 9 years people management (3 to 24 people) --Training /Execution / encourage member * Over 10 years production line support --SOP / cost down * Over 10 projects leader experience --cross-region communication (Germany/Japan/China /Malaysia) * 1 year MEMS design --simulation/process *Patents -- 6 patents Certified -- 4 patents on going Specialties --Passionate

Country

taiwan

City

taiwan

Industry

semiconductors

Skill

dram process, dram testing, physical failure analysis, electrical failure analysis, yield management, coventorware, mems design and simulation, semiconductors, testing, ic, soc, asic, failure analysis, electronics, product development, electrical engineering, yield, semiconductor industry, cmos

Experience

vishay intertechnology, inc.

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vishay intertechnology, inc.

winbond

department manager

winbond

2000-2 - 2013-7 · 13 yrs 6 mos
macronix international co., ltd

engineer

macronix international co., ltd

1999-8 - 2000-2 · 7 mos

* SOC product engineer * SOC testing * SRAM testing * SOC PFA

axelite

semiconductor process consult

axelite

2014-5 - 2015-2 · 10 mos

Mix-signal Product Dept. --Completed the process evaluation of the mix-signal IC by surveying Foundry Fabrication capability, comparing the benefits of cost (mask number, chip size), function (Device leakage, device type, Device Vt), quality (breakdown voltage, Qualification report) and Production Control. --Completed mix-signal IC evaluation & wafer start plan in UMC and VIS. A standard procedure was requested before mass production, including the tape out schedule, wafer start plan, assembly schedule and Evaluation plan.

fortuneadvance

manager

fortuneadvance

2013-8 - 2014-4 · 9 mos

* Mix-signal product Dept * Established the mix-signal IC QA plan and execution. * Performed the ESD failure analysis in MA-tek, , checked the test condition and ESD pad layout, and then found out the layout weakness point and come out with a solution. * Reduced the chip size by using the minimum layout rule to replace the standard cell. * Enhanced Yield Rate by performing Test result analysis and correct the test conditions to prevent over-kill issue. * ISO9000 build up team * Accomplished the ISO9000 certification plan

頎邦科技 chipbond

manager

頎邦科技 chipbond

2015-8 - Present · 11 yrs 2 mos

Education

national cental university r.o.c

national cental university r.o.c

electronics engineering

1993-1 - 1997-1 · 4 yrs 1 mo

Electrical Engineering Activities and Societies: 1993~1996 Social Service Club , President 1995~1996 EE Student Association ,Event support officer

tainan first high school

tainan first high school

1988-1 - 1991-1 · 3 yrs 1 mo

Senior High School Activities and Societies: computer club philately club

calvin yang's Contact Information

Email

******@***.com

Phone

(**) *** ****

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