Roy Y.
Uber TL (TPU System Software) @ Google
About
Systems Architect with 20+ years of experience engineering the boundary between hardware and software. Currently serving as the Uber Tech Lead for TPU System Software, defining the architecture that powers massive-scale AI training and inference. Core Expertise: AI Infrastructure: Architecting control planes, management planes, and manufacturing validation for multi-thousand chip clusters. Hardware-Software Codesign: Translating silicon and board constraints (power, thermal, SDC) into robust TPU supercomputer systems. Security & Orchestration: Former Kubernetes OS/Security Lead with deep expertise in confidential computing, Kubernetes, and kernel hardening. SKILLS & EXPERTISE Systems Programming: Go (Golang), C, C++, Bash, Python, User Space Drivers, Assembly. Cloud Native & Distributed Systems: Clustering, Kubernetes, CGroup v2, Device Plugins, CNI, CRI, Etcd, gRPC, Protobuf. Kernel & OS: Linux Kernel Tuning, Device Drivers (PCIe, I2C, GPIO, SATA, MTD), Container-Optimized OS (COS), Real-Time Linux (RTLinux), VxWorks. Hardware Interface: TPU/GPU Architecture, ASIC/FPGA Interaction, Board Bring-up, Power Sequencing (PMBus), Thermal Management, BMC/IPMI. Networking: 10/40/100GE Ethernet, PHY/MAC/SGMII, QoS, VNTAG, VLAN, TCP/IP, BGP/Routing. Security: Confidential Computing, Supply Chain Security, OS Hardening, TCG/SED Encryption, Vulnerability Management. Leadership & Strategy: End-to-End Product Delivery, New Product Introduction (NPI), Technical Roadmap Definition, Cross-Functional Alignment, Vendor/ODM Management, Engineering Mentorship. Objective: To leverage deep control-plane expertise and leadership in hardware-software codesign to architect the next generation of resilient, large-scale AI infrastructure.
United States
San Francisco Bay Area
Computer Software
COS, Etcd, Manufacturing, ML Systems, TPU, Fedora, CentOS, Golang, IPMI, Cluster Management, Hyper-Converged Storage System, Backup/Restore Software, Gentoo Linux, Chrome OS, Software Project Management, Security, Cross-functional Team Leadership, Go (Programming Language), Kubernetes, Google Kubernetes Engine (GKE)
Experience

Uber TL (TPU System Software)
Sunnyvale, CA
Serving as the Uber Tech Lead for the TPU System Software of Google’s next-generation TPU(TPU 8i). Technical Strategy: 1.) The TPU of 2026 (TPU 8i) - Architect for the end-to-end software stack, driving technical execution across 20+ teams, 5+ organizations to eliminate bottlenecks, fill gaps and ensure frictionless Datacenter deployments. Driving control plane, Management Plane and Data plane integration from chip to pod and from firmware to system. 2.) L11 Manufacturing: Defined the L11 Manufacturing Testing System, building qualification pipelines that accelerated datacenter turn-up velocity by ensuring "Plug-and-Play" readiness. Hands-on design on the architecture of the pipeline to push hundreds of SW packages from each team to system bundle, to Diagnostics, to Manufacturing Testing, and to JDMs 3.) Reliability: Lead for the Out-of-Band Management Network (BMCNet) on technical side, enhancing observability and installation reliability at fleet scale. BMCNet is the new management path from BMCs to Management Switch to TOR to Fleet. 4.) Innovation: Architect and design a Kubernetes cluster on Smartphones.

Tech Lead Manager(TLM) - Kubernetes/OS/Security
Sunnyvale, California, United States
Led the engineering strategy for OS, Storage, and Security across Google Distributed Cloud (GDC) Software Platforms, targeting the reduction of Kubernetes deployment complexity in Hybrid Cloud environments. Operating System Strategy: Defined the roadmap for GDC software across VMware, Bare Metal, and Multi-Cloud, resolving architectural conflicts between the Kubernetes control plane and the underlying Operating System to ensure consistent fleet behavior. Storage Architecture: Designed and implemented Storage Policy Based Management (SPBM) for Anthos on VMware. Managed the GDC Ready Storage Partner program and in-house qualification pipelines to proactively mitigate storage-layer risks before deployment. Security & Automation: Aligned security initiatives across multiple GKE flavors. Architected an automated vulnerability remediation system, eliminating manual patching toil and significantly reducing vulnerability exposure windows across the fleet. Products: - GDC/GKE on VMware and Bare metal(COS, Ubuntu)

Technical Lead - Container-Optimized OS (COS)
Sunnyvale, California, United States
Technical Lead for the specialized operating system powering Google Kubernetes Engine (GKE), CloudSQL, and Dataflow. Architecture Porting: Led the COS for ARM64 initiative from concept to launch, enabling GKE and GCP services to run on ARM-based instances (Tau T2A), winning Cloud Tech Impact Awards(2022). Kernel Lifecycle: Re-architected the kernel maintenance strategy, migrating from ChromeOS upstream to a server-grade LTS model, reducing patch overhead by >90% and improving fleet stability. Hybrid Cloud Enablement: Designed the COS Overlay architecture to decouple the OS from GCP-specific dependencies, enabling deployment on AWS, Azure, and vSphere for Anthos/GDC. Cross-Functional Leadership: Led execution across 20+ engineers and 10+ partner teams to deliver foundational OS capabilities for the entire GCP fleet. Products: - Container-Optimized OS - Google Kubernetes Engine

MTS - Secondary Storage Management
San Jose, California, United States
Founding member of the Platform Team, architecting the hardware, OS, and management plane for the Cohesity Data Platform from early-stage startup to global scale. Platform Control Plane: Architected and implemented the core Platform Management Daemon in Golang, responsible for the lifecycle management of Compute, Storage (Disk/RAID), and Networking across the cluster. Hardware Abstraction Layer (HAL): Designed the HAL to decouple software from underlying infrastructure, enabling a "Single OS" architecture that runs seamlessly across Bare Metal (Cisco/HPE/Dell), Virtual (vSphere/KVM), and Public Cloud (AWS/GCP/Azure). Security & Encryption: Engineered the Data-at-Rest security stack, implementing Self-Encrypting Drive (SED) management based on the TCG Opal protocol and driving OS hardening/kernel patching compliance. Networking Stack: Built the networking management subsystem from the ground up, handling complex L2/L3 configurations (NIC Bonding, VLANs, Bridges, VIPs, and Routes) dynamically via software. Hardware Strategy: Defined hardware specifications and roadmaps with ODM/OEM vendors. Implemented hardware observability (BMC, IPMI, sg3_utils) to expose physical component health to the software layer. Engineering Leadership: Bootstrapped and led a squad of 12+ engineers, scaling the platform team to 20+ developers across US, India, and Canada. Played a pivotal role in entering the China market, securing the company's first major regional customer. Products: - Cohesity C2000 Series Data Platform

Member Of Technical Staff - Primary Storage Platform
Mountain View
Storage Appliance Development: Developed platform software for the T800 Series VMStore, managing hardware enclosures via IPMI, SES (SCSI Enclosure Services), and SMBIOS. System Stability: Led critical debugging efforts for customer escalations, resolving complex race conditions in the storage stack for global customers. Products: - Tintri T800 Series VMStore Storage

Technical Leader - UCS & Nexus Switching
San Jose, California
Lead Systems Engineer for Cisco's billion-dollar revenue Server (UCS) and Core Switching (Nexus 7000) product lines. UCS Mini Chassis Management (Compute): 1.) Architect & Lead: Architected the chassis management software for the UCS Mini (UCS 6324), leading the full X86 Board Bring-up lifecycle. 2.) Kernel Subsystems: Optimized and tweaked critical Linux kernel subsystems including PCIe, I2C, GPIO, SATA, and MTD (Flash/NVRAM) to support custom hardware. 3.) Architecture Migration: Led the complex porting of the management stack from PowerPC (e300/e500) to X86, and from vanilla Linux to the hardened Nexus OS. 4.) Driver Modernization: Re-architected legacy kernel-mode drivers into User Space Drivers, significantly improving system stability and upgradeability. Subject Matter Expert: Recognized as the team's "Mr. I2C" for architecting the I2C MUX subsystem on Nexus OS and solving complex signaling issues. Nexus 7000 Line Card (Networking): 1. ASIC Driver Development: Designed and implemented the user-space ASIC driver for the high-density 6x40GE Line Card. Delivered critical data-plane features including QoS, VNTAG, VLAN Translation, and PTP/PONG (IEEE 1588). 2.) Optical Transceivers: Designed the FPGA-based QSFP Driver, enabling support for 40GE/100GE optics on the Nexus OS platform. 3.) Escalation Engineering: Served as the final point of escalation for Cisco TAC on critical customer outages related to platform stability and driver/hardware interaction Products: - Nexus 7000 switch; Product with billion-dollar revenue. - Cisco UCS 2200; Product with billion-dollar revenue https://www.cisco.com/c/en/us/products/collateral/servers-unified-computing/ucs-6300-series-fabric-interconnects/data_sheet_c78-675243.html - Cisco UCS 6324 Fabric Interconnect/MiniUCS https://www.cisco.com/c/en_ca/products/servers-unified-computing/ucs-mini/index.html .

Senior Platform Software Engineer - Edge Routing & Embedded
Sunnyvale, California
Network Device Drivers: Designed and implemented drivers for 20x1GE, 4x10GE XFP, and 40/100GE QSFP line cards. Wrote chip drivers for Optic Transceivers, PHYs, MACs, and Power/Clock ICs. Board Bring-Up: Led the bring-up of MIC and PMB boards, validating SGMII links, Auto-Negotiation, and ROM Monitor integration. System Software: Developed Chassis Management features on the Routing Engine (RE) and extended the Microkernel ROM Monitor capabilities. Products: - Juniper MX960/480/240 Series; Product with billion-dollar revenue Keywords: C, Power PC, Board Bring up, SFP/XFP/SFP+/CFP/CXP, I2C, MDIO, PHY, MAC, 10/40/100GE, Auto-Negotiation, RE/FPC/MIC, JUNOS, Chassis Management, Rom Monitor, Device DriverNetwork Device Drivers: Designed and implemented drivers for 20x1GE, 4x10GE XFP, and 40/100GE CFP line cards. Wrote chip drivers for Optic Transceivers, PHYs, MACs, and Power/Clock ICs.

Platform Software Engineer - VoIP Phone&Embedded
San Jose, California
Architected and delivered a next-generation VoIP phone system from concept to mass production, targeting the hospitality industry. System Architecture: Designed a novel Browser/Server architecture for embedded devices, enabling dynamic content delivery to hotel phones via an embedded web server and browser stack. Protocol Engineering: Owned the maintenance and debugging of the SIP Protocol Stack (RFC 3261). Led critical Interoperability Qualification efforts with major PBX vendors (Cisco, Avaya, Nortel, Alcatel-Lucent, Mitel), ensuring universal compatibility. Embedded Development (VxWorks): Developed low-level device drivers and board support packages (BSP) on VxWorks, including drivers for Touch Screens, Keypads, NVRAM, and software-based switching logic. Network Services: Implemented core provisioning and management protocols including TFTP, SNMP, and HTTP services. Products: - Teledex VoIP iPhone with/without screen Keywords: C, VoIP, SIP, RFC3261, VxWorks, IP PBX and Broadcom MIPS, Multi-threading

Research Assistant - HPC
Albuquerque, New Mexico
Research focus on Parallel Computing models and Dynamic Load Balancing strategies. Parallel Graph Processing (UPC): implemented and optimized parallel graph algorithms (e.g., Single-Source Shortest Path) using Unified Parallel C (UPC) and multi-threading. Load Balancing Algorithms: Designed and implemented simulation frameworks to evaluate statistical load balancing algorithms. Analyzed the trade-offs between task distribution granularity and system throughput to optimize parallel execution efficiency.

Software Engineer Intern - RTLinux
Socorro, New Mexico
Engineered a deterministic real-time audio pipeline on RTLinux to eliminate playback jitter caused by standard Linux scheduler preemption. Real-Time Kernel Threading: Developed a high-priority, hard real-time kernel thread to drive the AC97 Audio Driver, ensuring audio buffers were flushed with microsecond-level precision before yielding CPU control back to the general-purpose Linux kernel. User/Kernel IPC: Architected a lock-free mechanism using RT-FIFOs to stream decoded PCM data from user-space MP3 players directly into the real-time kernel context, bypassing standard system call overhead. Scheduler Bypass: Solved critical resource contention issues by ensuring the real-time audio thread could preempt standard Linux processes, guaranteeing skip-free playback even under heavy system load. Products: - FSMLabs Audio Player on RTLinuxFree (C/Linux) Keywords: RTLinux ,Linux, Multi-threading, Real-time OS

Software Engineer - 3G Wireless & Intelligent Network
Shanghai, China
Developed critical control-plane software for 3G Telecom infrastructure under strict CMM Level 5 engineering standards. Radio Resource Management (RRM): Developed real-time RRM algorithms for 3G WCDMA Radio Network Controllers (RNC) on VxWorks. Implemented critical logic for Load Balancing, Cell Resource Allocation, and Power Control based on 3GPP protocols (TS 25.331/433). Intelligent Networks (SCE): Engineered the Service Creation Environment (SCE), a C++/Unix visual programming tool for carrier-grade services. Key contributor to the software release that successfully qualified Huawei for the British Telecom vendor shortlist. Protocol Automation: Architected automated testing frameworks for CDMA core networks using TCL, leveraging deep expertise in telecom protocols (SS7, IS-41A, ASN.1) to validate system integration. Software Engineering: Executed software delivery under CMM Level 5 standards (the highest maturity level for software processes), rotating through roles in Configuration Management and Software Quality Measurement to ensure zero-defect delivery. Products: - Huawei CAT2000 CDMA 2000 AutoTest Tool - Huawei Service Creating Environment - Huawei BSC6800 Pre-REL 5/WCDMA; Product with billion-dollar revenue. Keywords: C/C++, TCL, Automation Testing, pSos/VxWorks, CDMA, WCDMA, RNC, CMM, Rational ClearCase, Software Engineering, 3GPP/3GPP2(TS 25.433)
Education
Stanford LEAD is a year-long, 9-course program which develops effective leaders who embody five core leadership competencies: critical analysis, self-awareness, interpersonal acumen, situational awareness, and holistic communication. These leaders complete coursework in key business fundamentals: finance, strategy, and critical analytical thinking, as well as elective coursework which equips them to successfully address and navigate the challenges and opportunities inherent in fostering and implementing change within their organizations. Throughout the program, participants exchange ideas and collaborate on projects with small teams of like-minded, like-motivated peers, and engage with world-renowned Stanford GSB faculty, Silicon Valley leaders, coaches, thought leaders, and luminaries through regular live events, discussions, and facilitated feedback.
Roy Y.'s Contact Information
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