brent wilson

principal engineer

About

Architect / Designer of multimedia and communications chips and systems o Consulting / Contracting – Contact for availability Advanced / Senior skills: o RTL - System Verilog, Verilog, VHDL o OVM / UVM - Constrained random stimulus, C++ golden reference models, assertions, coverage o Formal Verification - properties, functional models including RAM o ASIC, SoC and FPGA flow - Synthesis, DFT, STA, timing closure o Tools – Questasim, Modelsimc NCSim, Jasper, Design Compiler, Primetime, Goldtime, Altera, Xilinx o Scripting – Tcl, csh/grep/awk/sed o Agile Advanced / Senior design experience: o Video encoders and decoders including H.265 / HEVC, video DSP o Access networks, DSLAMs, routing gateways, ATM & IP networking, traffic managers, LTE baseband o PCIe transaction layer, Intel CCI (interface between processor and Altera FPGA), NVMe o AXI, SoC architectures, DDR & other fast interfaces, FIFOs, cache design, metastability o Embedded firmware & microcoding

Country

canada

City

belcarra

Industry

computer hardware

Skill

asic, soc, verilog, digital signal processors, fpga, vhdl, static timing analysis, video processing, systemverilog, rtl design, embedded systems, field programmable gate arrays, functional verification, hardware architecture, system on a chip, tcl, application specific integrated circuits, altera, firmware, mpeg2, h.265/hevc, system verilog, systemc, device drivers, formal verification, system c

Experience

software engineer

datek industries

1986-1 - 1989-1 · 3 yrs 1 mo

o Designed embedded firmware for 80x86 based remote terminal units including a custom multi-tasking RTOS, various device drivers, and IO subsystem modules

principal engineer

ebrisk video

2012-1 - 2013-1 · 1 yr 1 mo

o Digital design of H.265/HEVC video codecs o FPGA RTL

asic design

pmc-sierra

2011-1 - 2012-1 · 1 yr 1 mo

* o Deep submicron device top level STA * o Custom tcl and csh scripts, results analysis, interaction with layout, and timing closure * o DPLLs, SoC, source synchronous interfaces, multiple clock domains

imaging advanced development and research

dolby laboratories

2008-1 - 2011-1 · 3 yrs 1 mo

o High dynamic range and wide color gamut display prototypes, and color science perceptual-based video processing algorithms o Ground breaking HDR TV reference design for licensing package, and award winning postproduction technologies

asic product development

pmc-sierra

1998-1 - 2007-1 · 9 yrs 1 mo

* o Wrote lots of RTL including synthesis, DFT, STA, and verification * o Designed traffic manager queue engines, high speed memory interfaces * o Architected and implemented/reviewed top-level, IP cores, sub-systems, and sub-blocks * o Developed key technologies and processes for ASIC/SoCs and embedded firmware * o For part of the time, led large, complex, multi-site, multi-discipline, multi-cultural teams

video research and development

panasonic

1990-1 - 1998-1 · 8 yrs 1 mo

* o A lead architect of the video decoder SoC in the world's first DVD player * o RTL & embedded microcode for 3 video DSP SoCs, including world’s first MPEG2 codec chip * o 11 patents in area of MPEG codecs and video coding * o Represented Panasonic at MPEG4 implementations sub-group

principal engineer

wimatek systems

2015-1 - 2016-1 · 1 yr 1 mo

* o IoT LTE (cellular) SoC design * o Interface between RF IC and baseband IC * o Dual clock FIFO from scratch * o Specs, RTL, verification

principal engineer

microchip technology

2017-1 - Present · 9 yrs 9 mos

o Digital design of PCIe NVMe chips o Formal verification using JasperGold

rtl design and verification

altera

2016-1 - 2016-1 · 1 mo

* o Worked remotely (Vancouver) for teams in the UK * o H.265/HEVC video codec modules * o Cache-based motion compensation (encoder & decoder) * o Reconstructed picture pipeline * o Requirements, architecture/specs, implementation * o RTL, golden reference C++, directed & constrained random verification