Bilal Afzal

Formal Verification Engineer @ Cadence

About

Formal Verification Engineer with 2+ years at Cadence Design Systems, specialising in UCIe 2.0 MPG IP verification using JasperGold FPV & CSR and SVA/PSL assertions. Built 7 formal environments from scratch covering complex protocol blocks including credit-based flow control, TX/RX datapaths, and data link layer verification — delivering full coverage closure and sign-off.An early contributor to AI-driven verification methodology at team level, developing semi-autonomous agentic flows via Jasper MCP that reduced environment setup and property-writing overhead significantly. Also engineered a unified Formal + Simulation coverage merge pipeline with Jenkins CI, providing a single source of truth for sign-off across both verification domains.

Country

Ireland

City

Cork

Industry

Electrical & Electronic Manufacturing

Skill

Artificial Intelligence (AI), Jasper FPV, Jasper CSR, Formal Verification, Metric Driven Verification, Code Coverage, PCIe Protocol, CXL Protocol, UCIe Protocol, RTL Verification, verilog, System verilog, Universal Verification Methodology (UVM), Cadence Software, System on a Chip (SoC), Python (Programming Language), Modeling and Simulation, Circuit Analysis, Functional Verification, C (Programming Language)

Experience

Formal Verification Engineer

Cadence

2024-6 - Present · 2 yrs 4 mos

Cork

Teaching Assistant

University of Limerick

2023-9 - 2024-6 · 10 mos

Limerick, County Limerick, Ireland

Design Evaluation Engineer

Analog Devices

2023-5 - 2023-8 · 4 mos

Limerick, County Limerick, Ireland

Cooperating with Design and Test development teams to characterise units. Utilising top-of-the-range electronics test bench equipment via LabView to implement characterisation tests in a controlled environment. Processing the raw test data and presenting it to the Design team in a professional manner. Debugging PCBs by understanding the schematics and layout. Carrying out schematics using the Cadence Allegro tool.

Test Development Engineer (Precision Converters Group)

Analog Devices

2022-6 - 2023-1 · 8 mos

Raheen, County Limerick, Ireland

Operated the Teradyne UltraFlex ATE to test units during test program development. Carried out test board debug activities by interpreting the test board schematics and layout. Familiarity with VBA coding as well as the various Flex test instruments. Understanding the test sequence and correctly debugging the program or hardware. Experienced with data processing of large amounts of test data using R programming language.