Bhargava Sesha Sai Ram Sreekantham

When data is noisy but production decisions can’t wait, I turn early signals into actions that de‑risk new‑product ramps. In early NPI and LVM for memory products, that means connecting test data, bench diagnostics, and failure analysis to improve yield and enable safe, reliable exits into HVM. As a Package Device Product Engineer at Micron, I support NAND, UFS, and HSC programs across NPI and LVM phases, operating where assembly yield is still maturing and failure signatures are not yet fully characterized. In this role, I help guide engineering decisions by translating incomplete or evolving signals into actionable risk reduction. My day‑to‑day work spans yield and failure analysis using JMP‑based analytics, electrical bench diagnostics, and commonality studies, with a strong emphasis on separating true failure mechanisms from test or process artifacts and improving failure‑isolation fidelity early in the product lifecycle. I work closely with product engineering, test engineering, process integration, failure analysis, and quality teams to isolate assembly‑ and test‑driven issues, drive disposition, and manage risk often before full physical confirmation is available. Over time, I’ve learned that automation delivers the most value when applied selectively: accelerating learning, improving signal clarity, and strengthening readiness for sustained high‑volume manufacturing.